2021-09-04 17:56:49 +08:00
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/*
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* Copyright (C) 2021, lizhengyang
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2021-09-06 19:18:27 +08:00
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* 2021-09-02 lizhengyang first version
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2021-09-04 17:56:49 +08:00
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include "hc32_ddl.h"
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#include "drv_gpio.h"
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/* board configuration */
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#define SRAM_BASE 0x1FFF8000
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#define SRAM_SIZE 32*1024
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#define SRAM_END (SRAM_BASE + SRAM_SIZE)
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/* High speed sram. */
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="HEAP"
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#define HEAP_BEGIN (__segment_end("HEAP"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#endif
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#ifdef __ICCARM__
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/* Use *.icf ram symbal, to avoid hardcode.*/
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extern char __ICFEDIT_region_RAM_end__;
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#define HEAP_END (&__ICFEDIT_region_RAM_end__)
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#else
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#define HEAP_END SRAM_END
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#endif
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void rt_hw_board_init(void);
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void rt_hw_us_delay(rt_uint32_t us);
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#endif
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