257 lines
10 KiB
C
257 lines
10 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_i2c.h
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//
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// TITLE: I2C Register Definitions.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __F2837xD_I2C_H__
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#define __F2837xD_I2C_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// I2C Individual Register Bit Definitions:
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struct I2COAR_BITS { // bits description
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Uint16 OAR:10; // 9:0 I2C Own address
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Uint16 rsvd1:6; // 15:10 Reserved
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};
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union I2COAR_REG {
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Uint16 all;
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struct I2COAR_BITS bit;
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};
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struct I2CIER_BITS { // bits description
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Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable
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Uint16 NACK:1; // 1 No-acknowledgment interrupt enable
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Uint16 ARDY:1; // 2 Register-access-ready interrupt enable
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Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable
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Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable
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Uint16 SCD:1; // 5 Stop condition detected interrupt enable
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Uint16 AAS:1; // 6 Addressed as slave interrupt enable
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Uint16 rsvd1:9; // 15:7 Reserved
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};
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union I2CIER_REG {
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Uint16 all;
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struct I2CIER_BITS bit;
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};
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struct I2CSTR_BITS { // bits description
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Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit
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Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit.
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Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit
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Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit.
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Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit.
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Uint16 SCD:1; // 5 Stop condition detected bit.
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Uint16 rsvd1:2; // 7:6 Reserved
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Uint16 AD0:1; // 8 Address 0 bits
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Uint16 AAS:1; // 9 Addressed-as-slave bit
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Uint16 XSMT:1; // 10 Transmit shift register empty bit.
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Uint16 RSFULL:1; // 11 Receive shift register full bit.
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Uint16 BB:1; // 12 Bus busy bit.
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Uint16 NACKSNT:1; // 13 NACK sent bit.
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Uint16 SDIR:1; // 14 Slave direction bit
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Uint16 rsvd2:1; // 15 Reserved
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};
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union I2CSTR_REG {
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Uint16 all;
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struct I2CSTR_BITS bit;
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};
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struct I2CDRR_BITS { // bits description
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Uint16 DATA:8; // 7:0 Receive data
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union I2CDRR_REG {
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Uint16 all;
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struct I2CDRR_BITS bit;
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};
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struct I2CSAR_BITS { // bits description
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Uint16 SAR:10; // 9:0 Slave Address
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Uint16 rsvd1:6; // 15:10 Reserved
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};
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union I2CSAR_REG {
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Uint16 all;
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struct I2CSAR_BITS bit;
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};
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struct I2CDXR_BITS { // bits description
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Uint16 DATA:8; // 7:0 Transmit data
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union I2CDXR_REG {
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Uint16 all;
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struct I2CDXR_BITS bit;
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};
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struct I2CMDR_BITS { // bits description
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Uint16 BC:3; // 2:0 Bit count bits.
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Uint16 FDF:1; // 3 Free Data Format
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Uint16 STB:1; // 4 START Byte Mode
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Uint16 IRS:1; // 5 I2C Module Reset
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Uint16 DLB:1; // 6 Digital Loopback Mode
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Uint16 RM:1; // 7 Repeat Mode
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Uint16 XA:1; // 8 Expanded Address Mode
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Uint16 TRX:1; // 9 Transmitter Mode
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Uint16 MST:1; // 10 Master Mode
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Uint16 STP:1; // 11 STOP Condition
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Uint16 rsvd1:1; // 12 Reserved
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Uint16 STT:1; // 13 START condition bit
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Uint16 FREE:1; // 14 Debug Action
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Uint16 NACKMOD:1; // 15 NACK mode bit
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};
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union I2CMDR_REG {
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Uint16 all;
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struct I2CMDR_BITS bit;
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};
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struct I2CISRC_BITS { // bits description
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Uint16 INTCODE:3; // 2:0 Interrupt code bits.
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Uint16 rsvd1:5; // 7:3 Reserved
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Uint16 WRITE_ZEROS:4; // 11:8 Reserved
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Uint16 rsvd2:4; // 15:12 Reserved
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};
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union I2CISRC_REG {
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Uint16 all;
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struct I2CISRC_BITS bit;
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};
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struct I2CEMDR_BITS { // bits description
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Uint16 BC:1; // 0 Backwards compatibility mode
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Uint16 rsvd1:15; // 15:1 Reserved
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};
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union I2CEMDR_REG {
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Uint16 all;
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struct I2CEMDR_BITS bit;
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};
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struct I2CPSC_BITS { // bits description
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Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down
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Uint16 rsvd1:8; // 15:8 Reserved
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};
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union I2CPSC_REG {
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Uint16 all;
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struct I2CPSC_BITS bit;
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};
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struct I2CFFTX_BITS { // bits description
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Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level
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Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable
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Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear
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Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag
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Uint16 TXFFST:5; // 12:8 Transmit FIFO Status
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Uint16 TXFFRST:1; // 13 Transmit FIFO Reset
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Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable
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Uint16 rsvd1:1; // 15 Reserved
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};
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union I2CFFTX_REG {
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Uint16 all;
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struct I2CFFTX_BITS bit;
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};
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struct I2CFFRX_BITS { // bits description
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Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level
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Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable
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Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear
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Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag
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Uint16 RXFFST:5; // 12:8 Receive FIFO Status
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Uint16 RXFFRST:1; // 13 Receive FIFO Reset
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Uint16 rsvd1:2; // 15:14 Reserved
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};
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union I2CFFRX_REG {
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Uint16 all;
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struct I2CFFRX_BITS bit;
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};
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struct I2C_REGS {
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union I2COAR_REG I2COAR; // I2C Own address
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union I2CIER_REG I2CIER; // I2C Interrupt Enable
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union I2CSTR_REG I2CSTR; // I2C Status
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Uint16 I2CCLKL; // I2C Clock low-time divider
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Uint16 I2CCLKH; // I2C Clock high-time divider
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Uint16 I2CCNT; // I2C Data count
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union I2CDRR_REG I2CDRR; // I2C Data receive
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union I2CSAR_REG I2CSAR; // I2C Slave address
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union I2CDXR_REG I2CDXR; // I2C Data Transmit
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union I2CMDR_REG I2CMDR; // I2C Mode
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union I2CISRC_REG I2CISRC; // I2C Interrupt Source
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union I2CEMDR_REG I2CEMDR; // I2C Extended Mode
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union I2CPSC_REG I2CPSC; // I2C Prescaler
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Uint16 rsvd1[19]; // Reserved
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union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit
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union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive
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};
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//---------------------------------------------------------------------------
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// I2C External References & Function Declarations:
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//
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#ifdef CPU1
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extern volatile struct I2C_REGS I2caRegs;
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extern volatile struct I2C_REGS I2cbRegs;
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#endif
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#ifdef CPU2
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extern volatile struct I2C_REGS I2caRegs;
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extern volatile struct I2C_REGS I2cbRegs;
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#endif
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif
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//===========================================================================
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// End of file.
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//===========================================================================
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