2022-10-20 09:40:14 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2022-07-13 19:56:14 +08:00
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*
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2022-10-20 09:40:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2022-07-13 19:56:14 +08:00
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*
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2022-10-20 09:40:14 +08:00
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* Change Logs:
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* Date Author Notes
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* 2022-10-19 Nations first version
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2022-07-13 19:56:14 +08:00
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*/
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#include <rtdbg.h>
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#include "drv_dac.h"
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#ifdef RT_USING_DAC
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2022-10-20 09:40:14 +08:00
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#if defined(BSP_USING_DAC) || defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
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2022-07-13 19:56:14 +08:00
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static struct n32_dac_config dac_config[] =
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{
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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#ifdef BSP_USING_DAC
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{
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"dac",
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},
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#endif
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#endif
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2022-07-13 19:56:14 +08:00
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#ifdef BSP_USING_DAC1
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{
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"dac1",
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DAC_CHANNEL_1,
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},
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#endif
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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#ifdef BSP_USING_DAC2
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{
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"dac2",
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DAC_CHANNEL_2,
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},
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#endif
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};
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static struct n32_dac dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
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static void n32_dac_init(struct n32_dac_config *config)
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{
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DAC_InitType DAC_InitStructure;
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/* DAC Periph clock enable */
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RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_DAC, ENABLE);
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2022-10-20 09:40:14 +08:00
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2022-07-13 19:56:14 +08:00
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/* DAC channel Configuration */
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DAC_InitStructure.Trigger = DAC_TRG_SOFTWARE;
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DAC_InitStructure.WaveGen = DAC_WAVEGEN_NOISE;
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DAC_InitStructure.LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
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DAC_InitStructure.BufferOutput = DAC_BUFFOUTPUT_ENABLE;
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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2022-07-13 19:56:14 +08:00
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DAC_Init(config->dac_periph, &DAC_InitStructure);
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2022-10-20 09:40:14 +08:00
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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DAC_Init(&DAC_InitStructure);
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/* Enable DAC */
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DAC_Enable(ENABLE);
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/* Set DAC Channel DR12CH register */
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DAC_SetChData(DAC_ALIGN_R_12BIT, 4094);
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#endif
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2022-07-13 19:56:14 +08:00
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}
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static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
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{
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RT_ASSERT(device != RT_NULL);
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2022-07-23 11:53:42 +08:00
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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2022-07-13 19:56:14 +08:00
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DAC_Enable(channel, ENABLE);
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2022-10-20 09:40:14 +08:00
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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DAC_Enable(ENABLE);
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#endif
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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return RT_EOK;
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}
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static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
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2022-07-23 11:53:42 +08:00
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{
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2022-07-13 19:56:14 +08:00
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RT_ASSERT(device != RT_NULL);
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2022-07-23 11:53:42 +08:00
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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2022-07-13 19:56:14 +08:00
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DAC_Enable(channel, DISABLE);
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2022-10-20 09:40:14 +08:00
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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DAC_Enable(DISABLE);
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#endif
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2022-07-13 19:56:14 +08:00
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return RT_EOK;
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}
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static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
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2022-07-23 11:53:42 +08:00
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{
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RT_ASSERT(device != RT_NULL);
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2022-07-13 19:56:14 +08:00
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rt_uint16_t set_value = 0;
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set_value = (rt_uint16_t)*value;
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2022-07-23 11:53:42 +08:00
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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/* Start DAC Channel conversion by software */
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DAC_SoftTrgEnable(ENABLE);
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#endif
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if (set_value > 4096)
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2022-07-13 19:56:14 +08:00
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{
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set_value = 4096;
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}
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2022-07-23 11:53:42 +08:00
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
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2022-07-13 19:56:14 +08:00
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/* Start DAC Channel conversion by software */
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2022-10-20 09:40:14 +08:00
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if (channel == DAC_CHANNEL_1)
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{
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DAC_SetCh1Data(DAC_ALIGN_R_12BIT, set_value);
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DAC_SoftTrgEnable(DAC_CHANNEL_1, ENABLE);
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}
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else
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{
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DAC_SetCh2Data(DAC_ALIGN_R_12BIT, set_value);
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DAC_SoftTrgEnable(DAC_CHANNEL_2, ENABLE);
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}
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2022-10-20 09:40:14 +08:00
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#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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DAC_SetChData(DAC_ALIGN_R_12BIT, set_value);
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#endif
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2022-07-13 19:56:14 +08:00
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return RT_EOK;
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}
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static const struct rt_dac_ops n32_dac_ops =
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{
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.disabled = n32_dac_disabled,
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.enabled = n32_dac_enabled,
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.convert = n32_set_dac_value,
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};
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int rt_hw_dac_init(void)
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{
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2022-10-20 09:40:14 +08:00
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GPIO_InitType GPIO_InitStructure;
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2022-07-13 19:56:14 +08:00
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int result = RT_EOK;
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/* save dac name */
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char name_buf[5] = {'d', 'a', 'c', '0', 0};
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int i = 0;
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for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
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{
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/* dac init */
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dac_obj[i].config = &dac_config[i];
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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#if defined(BSP_USING_DAC)
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name_buf[3] = '\0';
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/* Enable GPIO clock */
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Config DAC chennel */
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GPIO_InitStructure.Pin = GPIO_PIN_4;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Input;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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#endif
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#endif
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#ifdef BSP_USING_DAC1
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2022-07-13 19:56:14 +08:00
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if (dac_obj[i].config->dac_periph == DAC_CHANNEL_1)
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{
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name_buf[3] = '1';
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2022-10-20 09:40:14 +08:00
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PA4 DAC1 */
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GPIO_InitStructure.Pin = GPIO_PIN_4;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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2022-07-13 19:56:14 +08:00
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}
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2022-10-20 09:40:14 +08:00
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2022-07-13 19:56:14 +08:00
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#endif
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2022-10-20 09:40:14 +08:00
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#ifdef BSP_USING_DAC2
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2022-07-13 19:56:14 +08:00
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if (dac_obj[i].config->dac_periph == DAC_CHANNEL_2)
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{
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name_buf[3] = '2';
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2022-10-20 09:40:14 +08:00
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PA5 DAC1 */
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GPIO_InitStructure.Pin = GPIO_PIN_5;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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2022-07-13 19:56:14 +08:00
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}
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#endif
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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/* register dac device */
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2022-10-20 09:40:14 +08:00
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n32_dac_init(&dac_config[i]);
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if (rt_hw_dac_register(&dac_obj[i].dac_device, name_buf, &n32_dac_ops, &dac_obj[i].config->dac_periph) == RT_EOK)
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{
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LOG_D("%s init success", name_buf);
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}
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else
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2022-07-13 19:56:14 +08:00
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{
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2022-10-20 09:40:14 +08:00
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LOG_E("%s register failed", name_buf);
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result = -RT_ERROR;
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2022-07-23 11:53:42 +08:00
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}
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2022-07-13 19:56:14 +08:00
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}
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return result;
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}
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INIT_DEVICE_EXPORT(rt_hw_dac_init);
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#endif /* defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2) */
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#endif /* RT_USING_DAC */
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