577 lines
19 KiB
C
577 lines
19 KiB
C
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/**
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******************************************************************************
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* @file system_stm32h7xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32h7xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32h7xx_system
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* @{
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*/
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/** @addtogroup STM32H7xx_System_Private_Includes
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* @{
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*/
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#include "stm32h7xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (CSI_VALUE)
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#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H7xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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on EVAL board as data memory */
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/*#define DATA_IN_ExtSRAM */
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/*#define DATA_IN_ExtSDRAM*/
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#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
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#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
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#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32H7xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H7xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 64000000;
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32H7xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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* configuration.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= RCC_CR_HSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
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RCC->CR &= (uint32_t)0xEAF6ED7F;
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x00000000;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x00000000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x00000000;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x00000000;
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x00000000;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal ITCMSRAM */
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#else
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SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock , it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
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* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
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*
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* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
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* 64 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t pllp = 2, pllsource = 0, pllm = 2 ,tmp, pllfracen =0 , hsivalue = 0;
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float fracn1, pllvco = 0 ;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
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break;
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case 0x08: /* CSI used as system clock source */
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SystemCoreClock = CSI_VALUE;
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break;
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case 0x10: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x18: /* PLL1 used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
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pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
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pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
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fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
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switch (pllsource)
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{
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case 0x00: /* HSI used as PLL clock source */
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
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pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
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break;
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case 0x01: /* CSI used as PLL clock source */
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pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
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break;
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case 0x02: /* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
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break;
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default:
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pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 );
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break;
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}
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pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ;
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SystemCoreClock = (uint32_t) (pllvco/pllp);
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break;
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default:
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SystemCoreClock = CSI_VALUE;
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break;
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}
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/* Compute HCLK frequency --------------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
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/* HCLK frequency */
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SystemCoreClock >>= tmp;
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}
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32h7xx.s before jump to main.
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* This function configures the external memories (SRAM/SDRAM)
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* This SRAM/SDRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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#if defined (DATA_IN_ExtSDRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register __IO uint32_t index;
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/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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clock */
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RCC->AHB4ENR |= 0x000001F8;
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x000000CC;
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GPIOD->AFR[1] = 0xCC000CCC;
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/* Configure PDx pins in Alternate function mode */
|
||
|
|
GPIOD->MODER = 0xAFEAFFFA;
|
||
|
|
/* Configure PDx pins speed to 50 MHz */
|
||
|
|
GPIOD->OSPEEDR = 0xA02A000A;
|
||
|
|
/* Configure PDx pins Output type to push-pull */
|
||
|
|
GPIOD->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PDx pins */
|
||
|
|
GPIOD->PUPDR = 0x55555505;
|
||
|
|
/* Connect PEx pins to FMC Alternate function */
|
||
|
|
GPIOE->AFR[0] = 0xC00000CC;
|
||
|
|
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||
|
|
/* Configure PEx pins in Alternate function mode */
|
||
|
|
GPIOE->MODER = 0xAAAABFFA;
|
||
|
|
/* Configure PEx pins speed to 50 MHz */
|
||
|
|
GPIOE->OSPEEDR = 0xAAAA800A;
|
||
|
|
/* Configure PEx pins Output type to push-pull */
|
||
|
|
GPIOE->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PEx pins */
|
||
|
|
GPIOE->PUPDR = 0x55554005;
|
||
|
|
/* Connect PFx pins to FMC Alternate function */
|
||
|
|
GPIOF->AFR[0] = 0x00CCCCCC;
|
||
|
|
GPIOF->AFR[1] = 0xCCCCC000;
|
||
|
|
/* Configure PFx pins in Alternate function mode */
|
||
|
|
GPIOF->MODER = 0xAABFFAAA;
|
||
|
|
/* Configure PFx pins speed to 50 MHz */
|
||
|
|
GPIOF->OSPEEDR = 0xAA800AAA;
|
||
|
|
/* Configure PFx pins Output type to push-pull */
|
||
|
|
GPIOF->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PFx pins */
|
||
|
|
GPIOF->PUPDR = 0x55400555;
|
||
|
|
/* Connect PGx pins to FMC Alternate function */
|
||
|
|
GPIOG->AFR[0] = 0x00CCCCCC;
|
||
|
|
GPIOG->AFR[1] = 0xC000000C;
|
||
|
|
/* Configure PGx pins in Alternate function mode */
|
||
|
|
GPIOG->MODER = 0xBFFEFAAA;
|
||
|
|
/* Configure PGx pins speed to 50 MHz */
|
||
|
|
GPIOG->OSPEEDR = 0x80020AAA;
|
||
|
|
/* Configure PGx pins Output type to push-pull */
|
||
|
|
GPIOG->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PGx pins */
|
||
|
|
GPIOG->PUPDR = 0x40010515;
|
||
|
|
/* Connect PHx pins to FMC Alternate function */
|
||
|
|
GPIOH->AFR[0] = 0xCCC00000;
|
||
|
|
GPIOH->AFR[1] = 0xCCCCCCCC;
|
||
|
|
/* Configure PHx pins in Alternate function mode */
|
||
|
|
GPIOH->MODER = 0xAAAAABFF;
|
||
|
|
/* Configure PHx pins speed to 50 MHz */
|
||
|
|
GPIOH->OSPEEDR = 0xAAAAA800;
|
||
|
|
/* Configure PHx pins Output type to push-pull */
|
||
|
|
GPIOH->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PHx pins */
|
||
|
|
GPIOH->PUPDR = 0x55555400;
|
||
|
|
/* Connect PIx pins to FMC Alternate function */
|
||
|
|
GPIOI->AFR[0] = 0xCCCCCCCC;
|
||
|
|
GPIOI->AFR[1] = 0x00000CC0;
|
||
|
|
/* Configure PIx pins in Alternate function mode */
|
||
|
|
GPIOI->MODER = 0xFFEBAAAA;
|
||
|
|
/* Configure PIx pins speed to 50 MHz */
|
||
|
|
GPIOI->OSPEEDR = 0x0028AAAA;
|
||
|
|
/* Configure PIx pins Output type to push-pull */
|
||
|
|
GPIOI->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PIx pins */
|
||
|
|
GPIOI->PUPDR = 0x00145555;
|
||
|
|
/*-- FMC Configuration ------------------------------------------------------*/
|
||
|
|
/* Enable the FMC interface clock */
|
||
|
|
(RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
|
||
|
|
/*SDRAM Timing and access interface configuration*/
|
||
|
|
/*LoadToActiveDelay = 2
|
||
|
|
ExitSelfRefreshDelay = 6
|
||
|
|
SelfRefreshTime = 4
|
||
|
|
RowCycleDelay = 6
|
||
|
|
WriteRecoveryTime = 2
|
||
|
|
RPDelay = 2
|
||
|
|
RCDDelay = 2
|
||
|
|
SDBank = FMC_SDRAM_BANK2
|
||
|
|
ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
|
||
|
|
RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
|
||
|
|
MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
|
||
|
|
InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
|
||
|
|
CASLatency = FMC_SDRAM_CAS_LATENCY_2
|
||
|
|
WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
|
||
|
|
SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
|
||
|
|
ReadBurst = FMC_SDRAM_RBURST_ENABLE
|
||
|
|
ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
|
||
|
|
|
||
|
|
FMC_Bank5_6->SDCR[0] = 0x00001800;
|
||
|
|
FMC_Bank5_6->SDCR[1] = 0x00000165;
|
||
|
|
FMC_Bank5_6->SDTR[0] = 0x00105000;
|
||
|
|
FMC_Bank5_6->SDTR[1] = 0x01010351;
|
||
|
|
|
||
|
|
/* SDRAM initialization sequence */
|
||
|
|
/* Clock enable command */
|
||
|
|
FMC_Bank5_6->SDCMR = 0x00000009;
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Delay */
|
||
|
|
for (index = 0; index<1000; index++);
|
||
|
|
|
||
|
|
/* PALL command */
|
||
|
|
FMC_Bank5_6->SDCMR = 0x0000000A;
|
||
|
|
timeout = 0xFFFF;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
FMC_Bank5_6->SDCMR = 0x000000EB;
|
||
|
|
timeout = 0xFFFF;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
|
||
|
|
FMC_Bank5_6->SDCMR = 0x0004400C;
|
||
|
|
timeout = 0xFFFF;
|
||
|
|
while((tmpreg != 0) && (timeout-- > 0))
|
||
|
|
{
|
||
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
|
|
}
|
||
|
|
/* Set refresh count */
|
||
|
|
tmpreg = FMC_Bank5_6->SDRTR;
|
||
|
|
FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
|
||
|
|
|
||
|
|
/* Disable write protection */
|
||
|
|
tmpreg = FMC_Bank5_6->SDCR[1];
|
||
|
|
FMC_Bank5_6->SDCR[1] = (tmpreg & 0xFFFFFDFF);
|
||
|
|
|
||
|
|
/*FMC controller Enable*/
|
||
|
|
FMC_Bank1->BTCR[0] |= 0x80000000;
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* DATA_IN_ExtSDRAM */
|
||
|
|
|
||
|
|
#if defined(DATA_IN_ExtSRAM)
|
||
|
|
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||
|
|
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||
|
|
RCC->AHB4ENR |= 0x00000078;
|
||
|
|
|
||
|
|
/* Connect PDx pins to FMC Alternate function */
|
||
|
|
GPIOD->AFR[0] = 0x00CCC0CC;
|
||
|
|
GPIOD->AFR[1] = 0xCCCCCCCC;
|
||
|
|
/* Configure PDx pins in Alternate function mode */
|
||
|
|
GPIOD->MODER = 0xAAAA0A8A;
|
||
|
|
/* Configure PDx pins speed to 100 MHz */
|
||
|
|
GPIOD->OSPEEDR = 0xFFFF0FCF;
|
||
|
|
/* Configure PDx pins Output type to push-pull */
|
||
|
|
GPIOD->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PDx pins */
|
||
|
|
GPIOD->PUPDR = 0x55550545;
|
||
|
|
|
||
|
|
/* Connect PEx pins to FMC Alternate function */
|
||
|
|
GPIOE->AFR[0] = 0xC00CC0CC;
|
||
|
|
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||
|
|
/* Configure PEx pins in Alternate function mode */
|
||
|
|
GPIOE->MODER = 0xAAAA828A;
|
||
|
|
/* Configure PEx pins speed to 100 MHz */
|
||
|
|
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
||
|
|
/* Configure PEx pins Output type to push-pull */
|
||
|
|
GPIOE->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PEx pins */
|
||
|
|
GPIOE->PUPDR = 0x55554145;
|
||
|
|
|
||
|
|
/* Connect PFx pins to FMC Alternate function */
|
||
|
|
GPIOF->AFR[0] = 0x00CCCCCC;
|
||
|
|
GPIOF->AFR[1] = 0xCCCC0000;
|
||
|
|
/* Configure PFx pins in Alternate function mode */
|
||
|
|
GPIOF->MODER = 0xAA000AAA;
|
||
|
|
/* Configure PFx pins speed to 100 MHz */
|
||
|
|
GPIOF->OSPEEDR = 0xFF000FFF;
|
||
|
|
/* Configure PFx pins Output type to push-pull */
|
||
|
|
GPIOF->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PFx pins */
|
||
|
|
GPIOF->PUPDR = 0x55000555;
|
||
|
|
|
||
|
|
/* Connect PGx pins to FMC Alternate function */
|
||
|
|
GPIOG->AFR[0] = 0x00CCCCCC;
|
||
|
|
GPIOG->AFR[1] = 0x000000C0;
|
||
|
|
/* Configure PGx pins in Alternate function mode */
|
||
|
|
GPIOG->MODER = 0x00200AAA;
|
||
|
|
/* Configure PGx pins speed to 100 MHz */
|
||
|
|
GPIOG->OSPEEDR = 0x00300FFF;
|
||
|
|
/* Configure PGx pins Output type to push-pull */
|
||
|
|
GPIOG->OTYPER = 0x00000000;
|
||
|
|
/* No pull-up, pull-down for PGx pins */
|
||
|
|
GPIOG->PUPDR = 0x00100555;
|
||
|
|
|
||
|
|
/*-- FMC/FSMC Configuration --------------------------------------------------*/
|
||
|
|
/* Enable the FMC/FSMC interface clock */
|
||
|
|
(RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
|
||
|
|
|
||
|
|
/* Configure and enable Bank1_SRAM2 */
|
||
|
|
FMC_Bank1->BTCR[4] = 0x00001091;
|
||
|
|
FMC_Bank1->BTCR[5] = 0x00110212;
|
||
|
|
FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
|
||
|
|
|
||
|
|
/*FMC controller Enable*/
|
||
|
|
FMC_Bank1->BTCR[0] |= 0x80000000;
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* DATA_IN_ExtSRAM */
|
||
|
|
}
|
||
|
|
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|