191 lines
10 KiB
C
191 lines
10 KiB
C
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/***********************************************************************************************************************
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* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
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*
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* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
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* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
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* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
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* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
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* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
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* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
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* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
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* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
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* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
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* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
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* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
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* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
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* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
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* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
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**********************************************************************************************************************/
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#ifndef R_SCI_UART_H
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#define R_SCI_UART_H
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/*******************************************************************************************************************//**
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* @addtogroup SCI_UART
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* @{
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**********************************************************************************************************************/
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/***********************************************************************************************************************
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* Includes
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**********************************************************************************************************************/
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#include "bsp_api.h"
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#include "r_uart_api.h"
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#include "r_sci_uart_cfg.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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/***********************************************************************************************************************
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* Macro definitions
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**********************************************************************************************************************/
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/**********************************************************************************************************************
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* Typedef definitions
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**********************************************************************************************************************/
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/** Enumeration for SCI clock source */
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typedef enum e_sci_clk_src
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{
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SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation
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SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
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SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
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SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
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} sci_clk_src_t;
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/** UART flow control mode definition */
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typedef enum e_flow_control
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{
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SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use SCI pin for RTS
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SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use SCI pin for CTS
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SCI_UART_FLOW_CONTROL_CTSRTS = 3U, ///< Use SCI pin for CTS, external pin for RTS
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} sci_uart_flow_control_t;
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/** UART instance control block. */
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typedef struct st_sci_uart_instance_ctrl
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{
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/* Parameters to control UART peripheral device */
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uint8_t fifo_depth; // FIFO depth of the UART channel
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uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise
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uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
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uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise
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uint32_t open; // Used to determine if the channel is configured
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bsp_io_port_pin_t flow_pin;
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/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
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uint8_t const * p_tx_src;
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/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
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uint32_t tx_src_bytes;
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/* Destination buffer pointer used for receiving data. */
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uint8_t const * p_rx_dest;
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/* Size of destination buffer pointer used for receiving data. */
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uint32_t rx_dest_bytes;
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/* Pointer to the configuration block. */
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uart_cfg_t const * p_cfg;
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/* Base register for this channel */
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R_SCI0_Type * p_reg;
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void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
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uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
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/* Pointer to context to be passed into callback function */
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void const * p_context;
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} sci_uart_instance_ctrl_t;
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/** Receive FIFO trigger configuration. */
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typedef enum e_sci_uart_rx_fifo_trigger
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{
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SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering
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SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
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} sci_uart_rx_fifo_trigger_t;
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/** Asynchronous Start Bit Edge Detection configuration. */
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typedef enum e_sci_uart_start_bit_detect
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{
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SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
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SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
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} sci_uart_start_bit_detect_t;
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/** Noise cancellation configuration. */
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typedef enum e_sci_uart_noise_cancellation
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{
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SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation
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SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation
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} sci_uart_noise_cancellation_t;
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/** Register settings to acheive a desired baud rate and modulation duty. */
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typedef struct st_baud_setting_t
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{
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union
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{
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uint8_t semr_baudrate_bits;
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struct
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{
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uint8_t : 2;
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uint8_t brme : 1; ///< Bit Rate Modulation Enable
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uint8_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1
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uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select
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uint8_t : 1;
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uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
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uint8_t : 1;
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};
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};
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uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
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uint8_t brr; ///< Bit Rate Register setting
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uint8_t mddr; ///< Modulation Duty Register setting
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} baud_setting_t;
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/** UART on SCI device Configuration */
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typedef struct st_sci_uart_extended_cfg
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{
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sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
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sci_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge
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sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
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baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
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sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used.
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bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
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sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin
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} sci_uart_extended_cfg_t;
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/**********************************************************************************************************************
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* Exported global variables
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**********************************************************************************************************************/
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/** @cond INC_HEADER_DEFS_SEC */
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/** Filled in Interface API structure for this Instance. */
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extern const uart_api_t g_uart_on_sci;
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/** @endcond */
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fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
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fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
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fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
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fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
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fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
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fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl);
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fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
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fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate,
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bool bitrate_modulation,
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uint32_t baud_rate_error_x_1000,
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baud_setting_t * const p_baud_setting);
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fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
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void ( * p_callback)(uart_callback_args_t *),
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void const * const p_context,
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uart_callback_args_t * const p_callback_memory);
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/*******************************************************************************************************************//**
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* @} (end addtogroup SCI_UART)
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**********************************************************************************************************************/
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif
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