328 lines
15 KiB
C
328 lines
15 KiB
C
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/*****************************************************************************
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* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
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*
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* This software is owned and published by:
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* Huada Semiconductor Co.,Ltd ("HDSC").
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*
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* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
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* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
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*
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* This software contains source code for use with HDSC
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* components. This software is licensed by HDSC to be adapted only
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* for use in systems utilizing HDSC components. HDSC shall not be
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* responsible for misuse or illegal use of this software for devices not
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* supported herein. HDSC is providing this software "AS IS" and will
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* not be responsible for issues arising from incorrect user implementation
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* of the software.
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*
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* Disclaimer:
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* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
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* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
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* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
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* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
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* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
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* WARRANTY OF NONINFRINGEMENT.
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* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
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* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
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* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
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* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
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* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
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* SAVINGS OR PROFITS,
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* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
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* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
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* FROM, THE SOFTWARE.
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*
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* This software may be replicated in part or whole for the licensed use,
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* with the restriction that this Disclaimer and Copyright notice must be
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* included with each copy of this software, whether used in part or whole,
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* at all times.
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*/
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/******************************************************************************/
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/** \file dma.h
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**
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** A detailed description is available at
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** @link DmacGroup Dmac description @endlink
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**
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** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac.
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**
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******************************************************************************/
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#ifndef __DMAC_H__
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#define __DMAC_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "ddl.h"
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup DmacGroup Direct Memory Access Control(DMAC)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief DMA Channel
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**
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******************************************************************************/
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typedef enum en_dma_channel
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{
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DmaCh0 = 0U, ///< DMA channel 0
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DmaCh1 = 1U, ///< DMA channel 1
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DmaChMax = 2U ///< DMA channel max
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} en_dma_channel_t;
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/**
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*******************************************************************************
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** \brief DMA priority
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**
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******************************************************************************/
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typedef enum en_dma_priority
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{
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DmaPriorityFix = 0U, ///< DMA channel priority fix (CH0>CH1)
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DmaPriorityLoop = 1U, ///< DMA channel priority loop
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} en_dma_priority_t;
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/**
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*******************************************************************************
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** \brief DMA transfer data width
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**
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******************************************************************************/
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typedef enum en_dma_transfer_width
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{
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Dma8Bit = 0U, ///< 8 bit transfer via DMA
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Dma16Bit = 1U, ///< 16 bit transfer via DMA
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Dma32Bit = 2U ///< 32 bit transfer via DMA
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} en_dma_transfer_width_t;
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/**
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*******************************************************************************
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** \brief DMA transfer mode
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**
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******************************************************************************/
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typedef enum en_dma_transfer_mode
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{
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DmaBlock = 0U, ///< block transfer via DMA
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DmaBurst = 1U, ///< burst transfer via DMA
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} en_dma_transfer_mode_t;
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/**
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*******************************************************************************
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** \brief DMA flag
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**
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******************************************************************************/
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typedef enum en_dma_stat
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{
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DEFAULT = 0U, ///< Reserve
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DmaAddOverflow = 1U, ///< DMA address overflow
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DmaHALT = 2U, ///< DMA HALT
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DmaAccSCRErr = 3U, ///< DMA access source address error
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DmaAccDestErr = 4U, ///< DMA access dest address error
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DmaTransferComplete = 5U, ///< DMA transfer complete
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DmaTransferPause = 7U, ///< DMA transfer pause
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} en_dma_stat_t;
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/**
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*******************************************************************************
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** \brief DMA address mode
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**
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******************************************************************************/
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typedef enum en_address_mode
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{
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AddressIncrease = 0U, ///< Address increased
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AddressFix = 1U, ///< Address fixed
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} en_address_mode_t;
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/**
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*******************************************************************************
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** \brief DMA repeat tranfer
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**
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******************************************************************************/
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typedef enum en_dma_msk
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{
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OneTranfer = 0U, ///< One Tranfer
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ContinuousTranfer = 1U, ///< Continuous Tranfer
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} en_dma_msk_t;
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/**
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*******************************************************************************
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** \brief DMA trigger selection
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**
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******************************************************************************/
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typedef enum stc_dma_trig_sel
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{
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SWTrig = 0U, ///< Select DMA software trig
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SPI0RXTrig = 32U, ///< Select DMA hardware trig 0
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SPI0TXTrig = 33U, ///< Select DMA hardware trig 1
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SPI1RXTrig = 34U, ///< Select DMA hardware trig 2
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SPI1TXTrig = 35U, ///< Select DMA hardware trig 3
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ADCJQRTrig = 36U, ///< Select DMA hardware trig 4
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ADCSQRTrig = 37U, ///< Select DMA hardware trig 5
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LCDTxTrig = 38U, ///< Select DMA hardware trig 6
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Uart0RxTrig = 40U, ///< Select DMA hardware trig 8
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Uart0TxTrig = 41U, ///< Select DMA hardware trig 9
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Uart1RxTrig = 42U, ///< Select DMA hardware trig 10
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Uart1TxTrig = 43U, ///< Select DMA hardware trig 11
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LpUart0RxTrig = 44U, ///< Select DMA hardware trig 12
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LpUart0TxTrig = 45U, ///< Select DMA hardware trig 13
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LpUart1RxTrig = 46U, ///< Select DMA hardware trig 14
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LpUart1TxTrig = 47U, ///< Select DMA hardware trig 15
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TIM0ATrig = 50U, ///< Select DMA hardware trig 18
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TIM0BTrig = 51U, ///< Select DMA hardware trig 19
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TIM1ATrig = 52U, ///< Select DMA hardware trig 20
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TIM1BTrig = 53U, ///< Select DMA hardware trig 21
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TIM2ATrig = 54U, ///< Select DMA hardware trig 22
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TIM2BTrig = 55U, ///< Select DMA hardware trig 23
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TIM3ATrig = 56U, ///< Select DMA hardware trig 24
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TIM3BTrig = 57U, ///< Select DMA hardware trig 25
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TIM4ATrig = 58U, ///< Select DMA hardware trig 26
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TIM4BTrig = 59U, ///< Select DMA hardware trig 27
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TIM5ATrig = 60U, ///< Select DMA hardware trig 28
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TIM5BTrig = 61U, ///< Select DMA hardware trig 29
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TIM6ATrig = 62U, ///< Select DMA hardware trig 30
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TIM6BTrig = 63U, ///< Select DMA hardware trig 31
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}en_dma_trig_sel_t;
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/**
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*******************************************************************************
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** \brief DMA interrupt selection
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**
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******************************************************************************/
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typedef struct stc_dma_irq
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{
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boolean_t TrnErrIrq; ///< Select DMA transfer error interrupt
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boolean_t TrnCpltIrq; ///< Select DMA transfer completion interrupt
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}stc_dma_irq_sel_t;
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/**
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*******************************************************************************
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** \brief DMA configuration
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**
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******************************************************************************/
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typedef struct stc_dma_config
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{
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en_dma_transfer_mode_t enMode;
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uint16_t u16BlockSize; ///< Transfer Block counter
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uint16_t u16TransferCnt; ///< Transfer counter
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en_dma_transfer_width_t enTransferWidth; ///< DMA transfer width (see #en_dma_transfer_width_t for details)
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en_address_mode_t enSrcAddrMode; ///< Source address mode(see #en_source_address_mode_t for details)
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en_address_mode_t enDstAddrMode; ///< Destination address mode(see #en_dest_address_mode_t for details)
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boolean_t bSrcAddrReloadCtl; ///< Source address reload(TRUE: reload;FALSE: reload forbidden)
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boolean_t bDestAddrReloadCtl; ///< Dest address reload(TRUE: reload;FALSE: reload forbidden)
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boolean_t bSrcBcTcReloadCtl; ///< Bc/Tc address reload(TRUE: reload;FALSE: reload forbidden)
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uint32_t u32SrcAddress; ///< Source address>
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uint32_t u32DstAddress; ///< Dest address>
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boolean_t bMsk; ///0: clear the bit (CONFA:ENS) after tarnfer;1: remain the bit (CONFA:ENS) after tarnfer
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en_dma_trig_sel_t enRequestNum; ///< DMA trigger request number
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} stc_dma_config_t;
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/**
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******************************************************************************
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** \brief DMA中断回调函数
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*****************************************************************************/
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typedef struct stc_dma_irq_calbakfn_pt
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{
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/*! Dma传输完成中断回调函数指针*/
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func_ptr_t pfnDma0TranferCompleteIrq;
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/*! Dma传输完成中断回调函数指针*/
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func_ptr_t pfnDma1TranferCompleteIrq;
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/*! Dma传输错误中断回调函数指针*/
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func_ptr_t pfnDma0TranferErrIrq;
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/*! Dma传输错误中断回调函数指针*/
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func_ptr_t pfnDma1TranferErrIrq;
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}stc_dma_irq_calbakfn_pt_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_config_t* pstcConfig);
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void Dma_SwTrigger(en_dma_channel_t enCh);
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void Dma_Enable(void);
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void Dma_Disable(void);
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void Dma_Start(en_dma_channel_t enCh);
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void Dma_Stop(en_dma_channel_t enCh);
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en_result_t Dma_EnableChannel(en_dma_channel_t enCh);
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en_result_t Dma_DisableChannel(en_dma_channel_t enCh);
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en_result_t Dma_SetTriggerSel(en_dma_channel_t enCh, en_dma_trig_sel_t enTrgSel);
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en_result_t Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address);
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en_result_t Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address);
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en_result_t Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize);
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en_result_t Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt);
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en_result_t Dma_SetSourceIncMode(en_dma_channel_t enCh, en_address_mode_t enMode);
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en_result_t Dma_SetDestinationIncMode(en_dma_channel_t enCh, en_address_mode_t enMode);
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en_result_t Dma_EnableSourceRload(en_dma_channel_t enCh);
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en_result_t Dma_DisableSourceRload(en_dma_channel_t enCh);
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en_result_t Dma_EnableDestinationRload(en_dma_channel_t enCh);
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en_result_t Dma_DisableDestinationRload(en_dma_channel_t enCh);
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en_result_t Dma_EnableContinusTranfer(en_dma_channel_t enCh);
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en_result_t Dma_DisableContinusTranfer(en_dma_channel_t enCh);
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en_result_t Dma_EnableBcTcReload(en_dma_channel_t enCh);
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en_result_t Dma_DisableBcTcReload(en_dma_channel_t enCh);
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void Dma_HaltTranfer(void);
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void Dma_RecoverTranfer(void);
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en_result_t Dma_PauseChannelTranfer(en_dma_channel_t enCh);
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en_result_t Dma_RecoverChannelTranfer(en_dma_channel_t enCh);
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en_result_t Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth);
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en_result_t Dma_SetChPriority(en_dma_priority_t enPrio);
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en_result_t Dma_EnableChannelIrq(en_dma_channel_t enCh);
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en_result_t Dma_DisableChannelIrq(en_dma_channel_t enCh);
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en_result_t Dma_EnableChannelErrIrq(en_dma_channel_t enCh);
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en_result_t Dma_DisableChannelErrIrq(en_dma_channel_t enCh);
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en_result_t Dma_ConfigIrq(en_dma_channel_t enCh,stc_dma_irq_sel_t* stcDmaIrqCfg,stc_dma_irq_calbakfn_pt_t* pstcDmaIrqCalbaks);
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en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh);
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void Dma_ClrStat(en_dma_channel_t enCh);
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//@} // DmacGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMAC_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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