2021-05-01 19:15:37 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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*/
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#ifndef __GIC_V3_H__
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#define __GIC_V3_H__
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#include <rthw.h>
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#include <board.h>
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#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \
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: "=r"(Rt) \
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: \
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: "memory")
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#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \
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: \
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: "r"(Rt) \
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: "memory")
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/* AArch32 System register interface to GICv3 */
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#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
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#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
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#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
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#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
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#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2"
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#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2"
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#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
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#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
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#define ICC_DIR "p15, 0, %0, c12, c11, 1"
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#define ICC_PMR "p15, 0, %0, c4, c6, 0"
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#define ICC_RPR "p15, 0, %0, c12, c11, 3"
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#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
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#define ICC_MCTLR "p15, 6, %0, c12, c12, 4"
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#define ICC_SRE "p15, 0, %0, c12, c12, 5"
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#define ICC_HSRE "p15, 4, %0, c12, c9, 5"
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#define ICC_MSRE "p15, 6, %0, c12, c12, 5"
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#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
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#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
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#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7"
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#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x)))
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#define ROUTED_TO_ALL (1)
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#define ROUTED_TO_SPEC (0)
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/** Macro to access the Distributor Control Register (GICD_CTLR)
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*/
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#define GICD_CTLR_RWP (1<<31)
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#define GICD_CTLR_E1NWF (1<<7)
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#define GICD_CTLR_DS (1<<6)
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#define GICD_CTLR_ARE_NS (1<<5)
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#define GICD_CTLR_ARE_S (1<<4)
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#define GICD_CTLR_ENGRP1S (1<<2)
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#define GICD_CTLR_ENGRP1NS (1<<1)
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#define GICD_CTLR_ENGRP0 (1<<0)
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/** Macro to access the Redistributor Control Register (GICR_CTLR)
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*/
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#define GICR_CTLR_UWP (1<<31)
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#define GICR_CTLR_DPG1S (1<<26)
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#define GICR_CTLR_DPG1NS (1<<25)
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#define GICR_CTLR_DPG0 (1<<24)
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#define GICR_CTLR_RWP (1<<3)
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#define GICR_CTLR_IR (1<<2)
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#define GICR_CTLR_CES (1<<1)
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#define GICR_CTLR_EnableLPI (1<<0)
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/** Macro to access the Generic Interrupt Controller Interface (GICC)
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*/
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#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U)
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#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U)
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#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U)
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#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU)
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#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U)
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#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U)
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#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U)
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#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU)
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/** Macro to access the Generic Interrupt Controller Distributor (GICD)
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*/
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#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
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#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U)
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#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
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#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
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#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
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#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
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#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
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#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
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#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
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#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
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#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
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#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
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#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U)
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#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
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#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
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#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U)
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#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U)
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#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4)
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/* SGI base address is at 64K offset from Redistributor base address */
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#define GIC_RSGI_OFFSET 0x10000
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/** Macro to access the Generic Interrupt Controller Redistributor (GICD)
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*/
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#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
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#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U)
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#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U)
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#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U)
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#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U)
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#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U)
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#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U)
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#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U)
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#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U)
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#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U)
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#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U)
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#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U)
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#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U)
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#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U)
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#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U)
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#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U)
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#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U)
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#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U)
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#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U)
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#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U)
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#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U)
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#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U)
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#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4)
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#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U)
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#define GIC_RSGI_AFF1_OFFSET 16
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#define GIC_RSGI_AFF2_OFFSET 32
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#define GIC_RSGI_AFF3_OFFSET 48
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rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list);
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rt_uint64_t get_main_cpu_affval(void);
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int arm_gic_get_active_irq(rt_uint32_t index);
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void arm_gic_ack(rt_uint32_t index, int irq);
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void arm_gic_mask(rt_uint32_t index, int irq);
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void arm_gic_umask(rt_uint32_t index, int irq);
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rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
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void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
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void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
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2021-10-13 11:02:01 +08:00
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void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config);
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2021-05-01 19:15:37 +08:00
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rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
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void arm_gic_clear_active(rt_uint32_t index, int irq);
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void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
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rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq);
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void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
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rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq);
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void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
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rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index);
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void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point);
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rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
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rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq);
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void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode);
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rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index);
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rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
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void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group);
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rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq);
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int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id);
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int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id);
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int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
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int arm_gic_cpu_init(rt_uint32_t index);
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int arm_gic_redist_init(rt_uint32_t index);
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void arm_gic_dump_type(rt_uint32_t index);
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void arm_gic_dump(rt_uint32_t index);
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void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value);
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rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index);
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void arm_gic_secondary_cpu_init(void);
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#endif
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