266 lines
7.0 KiB
ArmAsm
266 lines
7.0 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2010-01-25 Bernard first version
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* 2012-06-01 aozima set pendsv priority to 0xFF.
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* 2012-08-17 aozima fixed bug: store r8 - r11.
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* 2013-02-20 aozima port to gcc.
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-11-04 bright fixed hardfault bug for gcc.
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*/
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.cpu cortex-m0
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.fpu softvfp
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.syntax unified
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.thumb
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.text
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.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
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.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
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.equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
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.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
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#include "../rtconfig.h"
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#ifdef RT_USING_SMP
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.equ SIO_CPUID, 0xd0000000 /* CPUID */
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.global rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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MRS R0, PRIMASK
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CPSID I
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BX LR
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.global rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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MSR PRIMASK, R0
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BX LR
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* R0 --> from
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* R1 --> to
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*/
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.global rt_hw_context_switch_interrupt
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.type rt_hw_context_switch_interrupt, %function
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.global rt_hw_context_switch
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.type rt_hw_context_switch, %function
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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#ifndef RT_USING_SMP
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/* set rt_thread_switch_interrupt_flag to 1 */
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LDR R2, =rt_thread_switch_interrupt_flag
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LDR R3, [R2]
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CMP R3, #1
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BEQ _reswitch
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MOVS R3, #1
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STR R3, [R2]
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LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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STR R0, [R2]
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_reswitch:
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LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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STR R1, [R2]
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#else
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/* context_switch_to smp */
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PUSH {LR}
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BL __rt_cpu_switch
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POP {R2}
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#endif
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LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR R1, =NVIC_PENDSVSET
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STR R1, [R0]
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#ifndef RT_USING_SMP
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BX LR
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#else
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BX R2
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#endif
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/* R0 --> switch from thread stack
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* R1 --> switch to thread stack
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* psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
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*/
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.global PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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/* disable interrupt to protect context switch */
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MRS R2, PRIMASK
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CPSID I
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#ifndef RT_USING_SMP
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/* get rt_thread_switch_interrupt_flag */
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LDR R0, =rt_thread_switch_interrupt_flag
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#else
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LDR R0, =SIO_CPUID
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LDR R1, [R0]
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LDR R3, =rt_thread_switch_array
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CMP R1, #0
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BEQ cpu0_info
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ADDS R3, #12
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cpu0_info:
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MOV R0, R3
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#endif
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LDR R1, [R0]
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CMP R1, #0x00
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BEQ pendsv_exit /* pendsv already handled */
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/* clear rt_thread_switch_interrupt_flag to 0 */
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MOVS R1, #0
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STR R1, [R0]
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#ifndef RT_USING_SMP
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LDR R0, =rt_interrupt_from_thread
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#else
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ADDS R0, #4
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#endif
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LDR R1, [R0]
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CMP R1, #0x00
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BEQ switch_to_thread /* skip register save at the first time */
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MRS R1, PSP /* get from thread stack pointer */
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SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */
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LDR R0, [R0]
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STR R1, [R0] /* update from thread stack pointer */
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STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */
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MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */
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MOV R5, R9
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MOV R6, R10
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MOV R7, R11
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STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */
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switch_to_thread:
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#ifndef RT_USING_SMP
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LDR R1, =rt_interrupt_to_thread
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#else
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MOV R1, R3
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ADDS R1, #8
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#endif
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LDR R1, [R1]
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LDR R1, [R1] /* load thread stack pointer */
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LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */
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PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */
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LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */
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MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */
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MOV R9, R5
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MOV R10, R6
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MOV R11, R7
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POP {R4 - R7} /* pop {R4 - R7} from MSP */
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MSR PSP, R1 /* update stack pointer */
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pendsv_exit:
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/* restore interrupt */
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MSR PRIMASK, R2
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MOVS R0, #0x03
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RSBS R0, R0, #0x00
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BX R0
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* R0 --> to
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*/
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.global rt_hw_context_switch_to
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.type rt_hw_context_switch_to, %function
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rt_hw_context_switch_to:
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#ifndef RT_USING_SMP
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LDR R1, =rt_interrupt_to_thread
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STR R0, [R1]
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/* set from thread to 0 */
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LDR R1, =rt_interrupt_from_thread
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MOVS R0, #0
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STR R0, [R1]
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/* set interrupt flag to 1 */
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LDR R1, =rt_thread_switch_interrupt_flag
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MOVS R0, #1
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STR R0, [R1]
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#else
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/* context_switch_to smp */
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MOV R2,R1
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MOV R1,R0
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MOVS R0,#0
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BL __rt_cpu_switch
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#endif
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/* set the PendSV and SysTick exception priority */
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LDR R0, =NVIC_SHPR3
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LDR R1, =NVIC_PENDSV_PRI
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LDR R2, [R0,#0x00] /* read */
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ORRS R1, R1, R2 /* modify */
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STR R1, [R0] /* write-back */
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LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR R1, =NVIC_PENDSVSET
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STR R1, [R0]
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NOP
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/* restore MSP */
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LDR R0, =SCB_VTOR
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LDR R0, [R0]
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LDR R0, [R0]
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NOP
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MSR MSP, R0
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/* enable interrupts at processor level */
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CPSIE I
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/* ensure PendSV exception taken place before subsequent operation */
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DSB
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ISB
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/* never reach here! */
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/* compatible with old version */
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.global rt_hw_interrupt_thread_switch
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.type rt_hw_interrupt_thread_switch, %function
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rt_hw_interrupt_thread_switch:
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BX LR
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NOP
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.global HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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/* get current context */
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MRS R0, PSP /* get fault thread stack pointer */
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PUSH {LR}
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BL rt_hw_hard_fault_exception
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POP {PC}
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/*
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* rt_uint32_t rt_hw_interrupt_check(void);
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* R0 --> state
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*/
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.global rt_hw_interrupt_check
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.type rt_hw_interrupt_check, %function
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rt_hw_interrupt_check:
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MRS R0, IPSR
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BX LR
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