2022-05-06 09:28:21 +08:00
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/*
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2022-05-31 11:53:56 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
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2022-05-06 09:28:21 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include <rtdevice.h>
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#include <rthw.h>
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#ifdef RT_USING_SERIAL
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#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \
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defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \
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defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \
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defined(BSP_USING_UART10)
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#include "drv_usart.h"
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#include "board_config.h"
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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#define DMA_CH_REG(reg_base, ch) \
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(*(uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL)))
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#define DMA_TRANS_CNT(unit, ch) \
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(READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS)
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#define USART_TCI_ENABLE(unit) \
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SET_REG32_BIT(unit->CR1, USART_INT_TX_CPLT)
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#define UART_BAUDRATE_ERR_MAX (0.025F)
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2022-05-31 11:53:56 +08:00
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#if defined (HC32F460)
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#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd
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#elif defined (HC32F4A0)
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#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd
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#endif
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#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd
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#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd
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2022-05-06 09:28:21 +08:00
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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extern rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx);
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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#ifdef RT_SERIAL_USING_DMA
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static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
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#endif
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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enum
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{
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#ifdef BSP_USING_UART1
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UART1_INDEX,
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#endif
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#ifdef BSP_USING_UART2
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UART2_INDEX,
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#endif
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#ifdef BSP_USING_UART3
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UART3_INDEX,
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#endif
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#ifdef BSP_USING_UART4
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UART4_INDEX,
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#endif
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#ifdef BSP_USING_UART5
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UART5_INDEX,
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#endif
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#ifdef BSP_USING_UART6
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UART6_INDEX,
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#endif
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#ifdef BSP_USING_UART7
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UART7_INDEX,
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#endif
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#ifdef BSP_USING_UART8
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UART8_INDEX,
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#endif
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#ifdef BSP_USING_UART9
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UART9_INDEX,
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#endif
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#ifdef BSP_USING_UART10
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UART10_INDEX,
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#endif
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};
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static struct hc32_uart_config uart_config[] =
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{
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#ifdef BSP_USING_UART1
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UART1_CONFIG,
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#endif
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#ifdef BSP_USING_UART2
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UART2_CONFIG,
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#endif
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#ifdef BSP_USING_UART3
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UART3_CONFIG,
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#endif
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#ifdef BSP_USING_UART4
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UART4_CONFIG,
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#endif
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#ifdef BSP_USING_UART5
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UART5_CONFIG,
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#endif
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#ifdef BSP_USING_UART6
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UART6_CONFIG,
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#endif
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#ifdef BSP_USING_UART7
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UART7_CONFIG,
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#endif
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#ifdef BSP_USING_UART8
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UART8_CONFIG,
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#endif
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#ifdef BSP_USING_UART9
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UART9_CONFIG,
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#endif
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#ifdef BSP_USING_UART10
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UART10_CONFIG,
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#endif
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};
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static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct hc32_uart *uart;
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stc_usart_uart_init_t uart_init;
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RT_ASSERT(RT_NULL != cfg);
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RT_ASSERT(RT_NULL != serial);
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uart = rt_container_of(serial, struct hc32_uart, serial);
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USART_UART_StructInit(&uart_init);
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uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT;
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uart_init.u32Baudrate = cfg->baud_rate;
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uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK;
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2022-05-31 11:53:56 +08:00
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#if defined (HC32F4A0)
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2022-05-06 09:28:21 +08:00
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if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
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(CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance))
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2022-05-31 11:53:56 +08:00
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#elif defined (HC32F460)
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if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
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(CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
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#endif
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2022-05-06 09:28:21 +08:00
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{
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uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE;
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}
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switch (cfg->data_bits)
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{
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case DATA_BITS_8:
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uart_init.u32DataWidth = USART_DATA_WIDTH_8BIT;
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break;
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case DATA_BITS_9:
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uart_init.u32DataWidth = USART_DATA_WIDTH_9BIT;
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break;
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default:
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uart_init.u32DataWidth = USART_DATA_WIDTH_8BIT;
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break;
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}
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switch (cfg->stop_bits)
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{
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case STOP_BITS_1:
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uart_init.u32StopBit = USART_STOPBIT_1BIT;
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break;
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case STOP_BITS_2:
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uart_init.u32StopBit = USART_STOPBIT_2BIT;
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break;
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default:
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uart_init.u32StopBit = USART_STOPBIT_1BIT;
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break;
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}
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switch (cfg->parity)
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{
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case PARITY_NONE:
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uart_init.u32Parity = USART_PARITY_NONE;
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break;
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case PARITY_EVEN:
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uart_init.u32Parity = USART_PARITY_EVEN;
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break;
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case PARITY_ODD:
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uart_init.u32Parity = USART_PARITY_ODD;
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break;
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default:
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uart_init.u32Parity = USART_PARITY_NONE;
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break;
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}
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if (BIT_ORDER_LSB == cfg->bit_order)
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{
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uart_init.u32FirstBit = USART_FIRST_BIT_LSB;
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}
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else
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{
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uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
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}
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2022-05-31 11:53:56 +08:00
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#if defined (HC32F4A0)
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2022-05-06 09:28:21 +08:00
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switch (cfg->flowcontrol)
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{
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case RT_SERIAL_FLOWCONTROL_NONE:
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uart_init.u32HWFlowControl = USART_HW_FLOWCTRL_NONE;
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break;
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case RT_SERIAL_FLOWCONTROL_CTSRTS:
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uart_init.u32HWFlowControl = USART_HW_FLOWCTRL_RTS_CTS;
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break;
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default:
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uart_init.u32HWFlowControl = USART_HW_FLOWCTRL_NONE;
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break;
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}
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2022-05-31 11:53:56 +08:00
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#endif
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2022-05-06 09:28:21 +08:00
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#ifdef RT_SERIAL_USING_DMA
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uart->dma_rx_last_index = 0;
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#endif
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/* Enable USART clock */
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2022-05-31 11:53:56 +08:00
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FCG_USART_CLK(uart->config->clock, ENABLE);
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2022-05-06 09:28:21 +08:00
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if (RT_EOK != rt_hw_board_uart_init(uart->config->Instance))
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{
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return -RT_ERROR;
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}
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/* Configure UART */
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uint32_t u32Div;
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float32_t f32Error;
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int32_t i32Ret = LL_ERR;
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USART_DeInit(uart->config->Instance);
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USART_UART_Init(uart->config->Instance, &uart_init, NULL);
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for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++)
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{
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USART_SetClockDiv(uart->config->Instance, u32Div);
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if ((LL_OK == USART_SetBaudrate(uart->config->Instance, uart_init.u32Baudrate, &f32Error)) &&
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((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX)))
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{
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i32Ret = LL_OK;
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break;
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}
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}
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if (i32Ret != LL_OK)
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{
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return -RT_ERROR;
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}
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/* Enable error interrupt */
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NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
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2022-06-16 10:39:51 +08:00
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USART_FuncCmd(uart->config->Instance, USART_TX | USART_RX | USART_INT_RX, ENABLE);
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2022-05-06 09:28:21 +08:00
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return RT_EOK;
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}
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static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct hc32_uart *uart;
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rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
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RT_ASSERT(RT_NULL != serial);
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uart = rt_container_of(serial, struct hc32_uart, serial);
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RT_ASSERT(RT_NULL != uart->config->Instance);
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switch (cmd)
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{
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/* Disable interrupt */
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case RT_DEVICE_CTRL_CLR_INT:
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if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
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{
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NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
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USART_FuncCmd(uart->config->Instance, USART_INT_RX, DISABLE);
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INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
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}
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else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
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{
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NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num);
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USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
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INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
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}
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#ifdef RT_SERIAL_USING_DMA
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else if (RT_DEVICE_FLAG_DMA_RX == ctrl_arg)
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{
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NVIC_DisableIRQ(uart->config->dma_rx->irq_config.irq_num);
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}
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else if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg)
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{
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NVIC_DisableIRQ(uart->config->dma_tx->irq_config.irq_num);
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}
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#endif
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break;
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/* Enable interrupt */
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case RT_DEVICE_CTRL_SET_INT:
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if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
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{
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hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
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2022-05-31 11:53:56 +08:00
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USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
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2022-05-06 09:28:21 +08:00
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}
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else
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{
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hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE);
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2022-05-31 11:53:56 +08:00
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USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
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USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
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2022-05-06 09:28:21 +08:00
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}
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break;
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#ifdef RT_SERIAL_USING_DMA
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case RT_DEVICE_CTRL_CONFIG:
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hc32_dma_config(serial, ctrl_arg);
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break;
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#endif
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case RT_DEVICE_CTRL_CLOSE:
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USART_DeInit(uart->config->Instance);
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break;
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}
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return RT_EOK;
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}
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static int hc32_putc(struct rt_serial_device *serial, char c)
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{
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struct hc32_uart *uart;
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RT_ASSERT(RT_NULL != serial);
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uart = rt_container_of(serial, struct hc32_uart, serial);
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RT_ASSERT(RT_NULL != uart->config->Instance);
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if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
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{
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if (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET)
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{
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return -1;
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}
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}
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else
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{
|
|
|
|
/* Polling mode. */
|
|
|
|
while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET);
|
|
|
|
}
|
|
|
|
USART_WriteData(uart->config->Instance, c);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hc32_getc(struct rt_serial_device *serial)
|
|
|
|
{
|
|
|
|
int ch = -1;
|
|
|
|
struct hc32_uart *uart;
|
|
|
|
|
|
|
|
RT_ASSERT(RT_NULL != serial);
|
|
|
|
|
|
|
|
uart = rt_container_of(serial, struct hc32_uart, serial);
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->Instance);
|
|
|
|
if (SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL))
|
|
|
|
{
|
|
|
|
ch = (rt_uint8_t)USART_ReadData(uart->config->Instance);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ch;
|
|
|
|
}
|
|
|
|
|
|
|
|
static rt_size_t hc32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
|
|
|
|
{
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
struct hc32_uart *uart;
|
|
|
|
struct dma_config *uart_dma;
|
|
|
|
|
|
|
|
RT_ASSERT(RT_NULL != serial);
|
|
|
|
RT_ASSERT(RT_NULL != buf);
|
|
|
|
|
|
|
|
if (size == 0)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
uart = rt_container_of(serial, struct hc32_uart, serial);
|
|
|
|
if (RT_SERIAL_DMA_TX == direction)
|
|
|
|
{
|
|
|
|
uart_dma = uart->config->dma_tx;
|
|
|
|
if (RESET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_CPLT))
|
|
|
|
{
|
|
|
|
RT_ASSERT(0);
|
|
|
|
}
|
|
|
|
DMA_SetSrcAddr(uart_dma->Instance, uart_dma->channel, (uint32_t)buf);
|
|
|
|
DMA_SetTransCount(uart_dma->Instance, uart_dma->channel, size);
|
|
|
|
DMA_ChCmd(uart_dma->Instance, uart_dma->channel, ENABLE);
|
|
|
|
USART_FuncCmd(uart->config->Instance, USART_TX, ENABLE);
|
|
|
|
USART_FuncCmd(uart->config->Instance, USART_INT_TX_CPLT, ENABLE);
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart_rx_irq_handler(struct hc32_uart *uart)
|
|
|
|
{
|
|
|
|
RT_ASSERT(RT_NULL != uart);
|
|
|
|
|
|
|
|
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart_tx_irq_handler(struct hc32_uart *uart)
|
|
|
|
{
|
|
|
|
RT_ASSERT(RT_NULL != uart);
|
|
|
|
|
|
|
|
if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_INT_TX)
|
|
|
|
{
|
|
|
|
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart)
|
|
|
|
{
|
|
|
|
RT_ASSERT(RT_NULL != uart);
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->Instance);
|
|
|
|
|
|
|
|
if (SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_FRAME_ERR)))
|
|
|
|
{
|
|
|
|
USART_ReadData(uart->config->Instance);
|
|
|
|
}
|
|
|
|
USART_ClearStatus(uart->config->Instance, (USART_FLAG_PARITY_ERR | USART_FLAG_FRAME_ERR | USART_FLAG_OVERRUN));
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
|
|
|
|
{
|
|
|
|
struct hc32_uart *uart;
|
|
|
|
uint32_t cmp_val;
|
|
|
|
CM_TMR0_TypeDef *TMR0_Instance;
|
|
|
|
uint8_t ch;
|
|
|
|
uint32_t timeout_bits;
|
|
|
|
stc_tmr0_init_t stcTmr0Init;
|
|
|
|
|
|
|
|
RT_ASSERT(RT_NULL != serial);
|
|
|
|
uart = rt_container_of(serial, struct hc32_uart, serial);
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->Instance);
|
|
|
|
|
|
|
|
TMR0_Instance = uart->config->rx_timeout->TMR0_Instance;
|
|
|
|
ch = uart->config->rx_timeout->channel;
|
|
|
|
timeout_bits = uart->config->rx_timeout->timeout_bits;
|
2022-05-31 11:53:56 +08:00
|
|
|
#if defined (HC32F460)
|
|
|
|
if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance))
|
|
|
|
{
|
|
|
|
RT_ASSERT(TMR0_CH_A == ch);
|
|
|
|
}
|
|
|
|
else if ((CM_USART2 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
|
|
|
|
{
|
|
|
|
RT_ASSERT(TMR0_CH_B == ch);
|
|
|
|
}
|
|
|
|
#elif defined (HC32F4A0)
|
2022-05-06 09:28:21 +08:00
|
|
|
if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance))
|
|
|
|
{
|
|
|
|
RT_ASSERT(TMR0_CH_A == ch);
|
|
|
|
}
|
|
|
|
else if ((CM_USART2 == uart->config->Instance) || (CM_USART7 == uart->config->Instance))
|
|
|
|
{
|
|
|
|
RT_ASSERT(TMR0_CH_B == ch);
|
|
|
|
}
|
2022-05-31 11:53:56 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE);
|
2022-05-06 09:28:21 +08:00
|
|
|
|
|
|
|
/* TIMER0 basetimer function initialize */
|
|
|
|
TMR0_DeInit(TMR0_Instance);
|
|
|
|
TMR0_SetCountValue(TMR0_Instance, ch, 0U);
|
|
|
|
TMR0_StructInit(&stcTmr0Init);
|
|
|
|
stcTmr0Init.u32ClockDiv = TMR0_CLK_DIV1;
|
|
|
|
stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_XTAL32;
|
|
|
|
if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDiv)
|
|
|
|
{
|
|
|
|
cmp_val = (timeout_bits - 4UL);
|
|
|
|
}
|
|
|
|
else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDiv)
|
|
|
|
{
|
|
|
|
cmp_val = (timeout_bits / 2UL - 2UL);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS)) - 1UL);
|
|
|
|
}
|
|
|
|
DDL_ASSERT(cmp_val <= 0xFFFFUL);
|
|
|
|
stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val);
|
|
|
|
TMR0_Init(TMR0_Instance, ch, &stcTmr0Init);
|
|
|
|
TMR0_HWStartCondCmd(TMR0_Instance, ch, ENABLE);
|
|
|
|
TMR0_HWClearCondCmd(TMR0_Instance, ch, ENABLE);
|
|
|
|
/* Clear compare flag */
|
|
|
|
TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << ch));
|
|
|
|
|
|
|
|
NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num);
|
|
|
|
USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT);
|
|
|
|
USART_FuncCmd(uart->config->Instance, (USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT), ENABLE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|
|
|
{
|
|
|
|
struct hc32_uart *uart;
|
|
|
|
stc_dma_init_t dma_init;
|
|
|
|
struct dma_config *uart_dma;
|
|
|
|
|
|
|
|
RT_ASSERT(RT_NULL != serial);
|
|
|
|
|
|
|
|
uart = rt_container_of(serial, struct hc32_uart, serial);
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->Instance);
|
|
|
|
if (RT_DEVICE_FLAG_DMA_RX == flag)
|
|
|
|
{
|
|
|
|
stc_dma_llp_init_t llp_init;
|
|
|
|
struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
|
|
|
|
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->rx_timeout->TMR0_Instance);
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
|
|
|
|
|
|
|
|
uart_dma = uart->config->dma_rx;
|
|
|
|
/* Initialization uart rx timeout for DMA */
|
|
|
|
hc32_uart_rx_timeout(serial);
|
|
|
|
/* Enable DMA clock */
|
2022-05-31 11:53:56 +08:00
|
|
|
FCG_DMA_CLK(uart_dma->clock, ENABLE);
|
2022-05-06 09:28:21 +08:00
|
|
|
DMA_ChCmd(uart_dma->Instance, uart_dma->channel, DISABLE);
|
|
|
|
|
|
|
|
/* Initialize DMA */
|
|
|
|
DMA_StructInit(&dma_init);
|
|
|
|
dma_init.u32IntEn = DMA_INT_ENABLE;
|
|
|
|
dma_init.u32SrcAddr = ((uint32_t)(&uart->config->Instance->DR) + 2UL);
|
|
|
|
dma_init.u32DestAddr = (uint32_t)rx_fifo->buffer;
|
|
|
|
dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT;
|
|
|
|
dma_init.u32BlockSize = 1UL;
|
|
|
|
dma_init.u32TransCount = serial->config.bufsz;
|
|
|
|
dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX;
|
|
|
|
dma_init.u32DestAddrInc = DMA_DEST_ADDR_INC;
|
|
|
|
DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init);
|
|
|
|
|
|
|
|
/* Initialize LLP */
|
|
|
|
llp_init.u32State = DMA_LLP_ENABLE;
|
|
|
|
llp_init.u32Mode = DMA_LLP_WAIT;
|
2022-06-09 14:32:37 +08:00
|
|
|
llp_init.u32Addr = (uint32_t)&uart->config->llp_desc;
|
2022-05-06 09:28:21 +08:00
|
|
|
DMA_LlpInit(uart_dma->Instance, uart_dma->channel, &llp_init);
|
|
|
|
|
|
|
|
/* Configure LLP descriptor */
|
2022-06-09 14:32:37 +08:00
|
|
|
uart->config->llp_desc.SARx = dma_init.u32SrcAddr;
|
|
|
|
uart->config->llp_desc.DARx = dma_init.u32DestAddr;
|
|
|
|
uart->config->llp_desc.DTCTLx = (dma_init.u32TransCount << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS);
|
|
|
|
uart->config->llp_desc.LLPx = (uint32_t)&uart->config->llp_desc;
|
|
|
|
uart->config->llp_desc.CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | \
|
2022-05-06 09:28:21 +08:00
|
|
|
llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn);
|
|
|
|
|
|
|
|
/* Enable DMA interrupt */
|
|
|
|
NVIC_EnableIRQ(uart->config->dma_rx->irq_config.irq_num);
|
|
|
|
/* Enable DMA module */
|
|
|
|
DMA_Cmd(uart_dma->Instance, ENABLE);
|
|
|
|
AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event);
|
|
|
|
DMA_ChCmd(uart_dma->Instance, uart_dma->channel, ENABLE);
|
|
|
|
}
|
|
|
|
else if (RT_DEVICE_FLAG_DMA_TX == flag)
|
|
|
|
{
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->dma_tx->Instance);
|
|
|
|
|
|
|
|
uart_dma = uart->config->dma_tx;
|
|
|
|
/* Enable DMA clock */
|
2022-05-31 11:53:56 +08:00
|
|
|
FCG_DMA_CLK(uart_dma->clock, ENABLE);
|
2022-05-06 09:28:21 +08:00
|
|
|
DMA_ChCmd(uart_dma->Instance, uart_dma->channel, DISABLE);
|
|
|
|
|
|
|
|
/* Initialize DMA */
|
|
|
|
DMA_StructInit(&dma_init);
|
|
|
|
dma_init.u32IntEn = DMA_INT_DISABLE;
|
|
|
|
dma_init.u32SrcAddr = 0UL;
|
|
|
|
dma_init.u32DestAddr = (uint32_t)(&uart->config->Instance->DR);
|
|
|
|
dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT;
|
|
|
|
dma_init.u32BlockSize = 1UL;
|
|
|
|
dma_init.u32TransCount = 0UL;
|
|
|
|
dma_init.u32SrcAddrInc = DMA_SRC_ADDR_INC;
|
|
|
|
dma_init.u32DestAddrInc = DMA_DEST_ADDR_FIX;
|
|
|
|
DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init);
|
|
|
|
|
|
|
|
/* Enable DMA module */
|
|
|
|
DMA_Cmd(uart_dma->Instance, ENABLE);
|
|
|
|
AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event);
|
|
|
|
USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_CPLT, DISABLE);
|
|
|
|
NVIC_EnableIRQ(uart->config->tc_irq->irq_config.irq_num);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-07-14 14:11:54 +08:00
|
|
|
#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \
|
|
|
|
defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || defined(BSP_UART7_RX_USING_DMA)
|
2022-05-06 09:28:21 +08:00
|
|
|
static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart)
|
|
|
|
{
|
|
|
|
struct rt_serial_device *serial;
|
|
|
|
rt_size_t recv_len;
|
|
|
|
rt_base_t level;
|
|
|
|
|
|
|
|
RT_ASSERT(RT_NULL != uart);
|
|
|
|
RT_ASSERT(RT_NULL != uart->config->Instance);
|
|
|
|
|
|
|
|
serial = &uart->serial;
|
|
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
recv_len = serial->config.bufsz - uart->dma_rx_last_index;
|
|
|
|
uart->dma_rx_last_index = 0UL;
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
if (recv_len)
|
|
|
|
{
|
|
|
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
|
|
|
|
{
|
|
|
|
rt_base_t level;
|
|
|
|
rt_size_t cnt;
|
|
|
|
rt_size_t recv_len;
|
|
|
|
rt_size_t recv_total_index;
|
|
|
|
|
|
|
|
cnt = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);
|
|
|
|
recv_total_index = uart->serial.config.bufsz - cnt;
|
|
|
|
if (0UL != recv_total_index)
|
|
|
|
{
|
|
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
recv_len = recv_total_index - uart->dma_rx_last_index;
|
|
|
|
uart->dma_rx_last_index = recv_total_index;
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
|
|
|
|
if (recv_len)
|
|
|
|
{
|
|
|
|
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
TMR0_Stop(uart->config->rx_timeout->TMR0_Instance, uart->config->rx_timeout->channel);
|
|
|
|
USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT);
|
|
|
|
}
|
2022-07-14 14:11:54 +08:00
|
|
|
#endif
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-07-14 14:11:54 +08:00
|
|
|
#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \
|
|
|
|
defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || defined(BSP_UART7_TX_USING_DMA)
|
2022-05-06 09:28:21 +08:00
|
|
|
static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
|
|
|
|
{
|
|
|
|
RT_ASSERT(uart != RT_NULL);
|
|
|
|
|
|
|
|
DMA_ClearTransCompleteStatus(uart->config->dma_tx->Instance, (DMA_FLAG_TC_CH0 | DMA_FLAG_BTC_CH0) << uart->config->dma_tx->channel);
|
|
|
|
USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE);
|
|
|
|
if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_DMA_TX)
|
|
|
|
{
|
|
|
|
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2022-07-14 14:11:54 +08:00
|
|
|
#endif
|
2022-05-06 09:28:21 +08:00
|
|
|
|
|
|
|
#if defined(BSP_USING_UART1)
|
|
|
|
static void hc32_uart1_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart1_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART1_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart1_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
|
|
#if defined(BSP_UART1_RX_USING_DMA)
|
|
|
|
static void hc32_uart1_rxto_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxto_irq_handler(&uart_obj[UART1_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart1_dma_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_dma_rx_irq_handler(&uart_obj[UART1_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART1_RX_USING_DMA */
|
|
|
|
|
|
|
|
#if defined(BSP_UART1_TX_USING_DMA)
|
|
|
|
static void hc32_uart1_tc_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART1_RX_USING_DMA */
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART1 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART2)
|
|
|
|
static void hc32_uart2_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART2_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart2_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART2_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart2_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART2_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
|
|
#if defined(BSP_UART2_TX_USING_DMA)
|
|
|
|
static void hc32_uart2_tc_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tc_irq_handler(&uart_obj[UART2_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART2_TX_USING_DMA */
|
|
|
|
|
|
|
|
#if defined(BSP_UART2_RX_USING_DMA)
|
|
|
|
static void hc32_uart2_rxto_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxto_irq_handler(&uart_obj[UART2_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart2_dma_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_dma_rx_irq_handler(&uart_obj[UART2_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART2_RX_USING_DMA */
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART2 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART3)
|
|
|
|
static void hc32_uart3_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART3_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart3_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART3_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart3_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART3_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
2022-05-31 11:53:56 +08:00
|
|
|
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
|
|
#if defined(BSP_UART3_TX_USING_DMA)
|
|
|
|
static void hc32_uart3_tc_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tc_irq_handler(&uart_obj[UART3_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART3_TX_USING_DMA */
|
|
|
|
|
|
|
|
#if defined(BSP_UART3_RX_USING_DMA)
|
|
|
|
static void hc32_uart3_rxto_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxto_irq_handler(&uart_obj[UART3_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart3_dma_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_dma_rx_irq_handler(&uart_obj[UART3_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART3_RX_USING_DMA */
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
2022-05-06 09:28:21 +08:00
|
|
|
#endif /* BSP_USING_UART3 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART4)
|
|
|
|
static void hc32_uart4_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART4_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart4_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART4_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart4_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART4_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
2022-05-31 11:53:56 +08:00
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
|
|
#if defined(BSP_UART4_TX_USING_DMA)
|
|
|
|
static void hc32_uart4_tc_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tc_irq_handler(&uart_obj[UART4_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART4_TX_USING_DMA */
|
|
|
|
|
|
|
|
#if defined(BSP_UART4_RX_USING_DMA)
|
|
|
|
static void hc32_uart4_rxto_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxto_irq_handler(&uart_obj[UART4_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart4_dma_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_dma_rx_irq_handler(&uart_obj[UART4_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART4_RX_USING_DMA */
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
2022-05-06 09:28:21 +08:00
|
|
|
#endif /* BSP_USING_UART4 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART5)
|
|
|
|
static void hc32_uart5_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART5_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart5_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART5_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart5_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART5_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART5 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART6)
|
|
|
|
static void hc32_uart6_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART6_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart6_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART6_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart6_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART6_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
|
|
#if defined(BSP_UART6_TX_USING_DMA)
|
|
|
|
static void hc32_uart6_tc_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tc_irq_handler(&uart_obj[UART6_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART6_TX_USING_DMA */
|
|
|
|
|
|
|
|
#if defined(BSP_UART6_RX_USING_DMA)
|
|
|
|
static void hc32_uart6_rxto_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxto_irq_handler(&uart_obj[UART6_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart6_dma_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_dma_rx_irq_handler(&uart_obj[UART6_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART6_RX_USING_DMA */
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART6 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART7)
|
|
|
|
static void hc32_uart7_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART7_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart7_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART7_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart7_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART7_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(RT_SERIAL_USING_DMA)
|
|
|
|
#if defined(BSP_UART7_TX_USING_DMA)
|
|
|
|
static void hc32_uart7_tc_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tc_irq_handler(&uart_obj[UART7_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART7_TX_USING_DMA */
|
|
|
|
|
|
|
|
#if defined(BSP_UART7_RX_USING_DMA)
|
|
|
|
static void hc32_uart7_rxto_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxto_irq_handler(&uart_obj[UART7_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart7_dma_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_dma_rx_irq_handler(&uart_obj[UART7_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_UART7_RX_USING_DMA */
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART7 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART8)
|
|
|
|
static void hc32_uart8_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART8_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart8_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART8_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart8_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART8_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART8 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART9)
|
|
|
|
static void hc32_uart9_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART9_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart9_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART9_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart9_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART9_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART9 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART10)
|
|
|
|
static void hc32_uart10_rx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rx_irq_handler(&uart_obj[UART10_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart10_tx_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_tx_irq_handler(&uart_obj[UART10_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hc32_uart10_rxerr_irq_handler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
hc32_uart_rxerr_irq_handler(&uart_obj[UART10_INDEX]);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART10 */
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief This function gets dma witch uart used infomation include unit,
|
|
|
|
* channel, interrupt etc.
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
static void hc32_uart_get_dma_info(void)
|
|
|
|
{
|
|
|
|
#ifdef BSP_USING_UART1
|
|
|
|
uart_obj[UART1_INDEX].uart_dma_flag = 0;
|
|
|
|
#ifdef BSP_UART1_RX_USING_DMA
|
|
|
|
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
|
|
|
|
static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG;
|
|
|
|
uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler;
|
|
|
|
uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler;
|
|
|
|
uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout;
|
|
|
|
uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_UART1_TX_USING_DMA
|
|
|
|
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
|
|
|
|
uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
|
|
|
|
static struct hc32_uart_irq_config uart1_tc_irq = UART1_TX_CPLT_CONFIG;
|
|
|
|
uart1_tc_irq.irq_callback = hc32_uart1_tc_irq_handler;
|
|
|
|
uart_config[UART1_INDEX].tc_irq = &uart1_tc_irq;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef BSP_USING_UART2
|
|
|
|
uart_obj[UART2_INDEX].uart_dma_flag = 0;
|
|
|
|
#ifdef BSP_UART2_RX_USING_DMA
|
|
|
|
uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
|
|
|
|
static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG;
|
|
|
|
uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler;
|
|
|
|
uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler;
|
|
|
|
uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout;
|
|
|
|
uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_UART2_TX_USING_DMA
|
|
|
|
uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
|
|
|
|
uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
|
|
|
|
static struct hc32_uart_irq_config uart2_tc_irq = UART2_TX_CPLT_CONFIG;
|
|
|
|
uart2_tc_irq.irq_callback = hc32_uart2_tc_irq_handler;
|
|
|
|
uart_config[UART2_INDEX].tc_irq = &uart2_tc_irq;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2022-05-31 11:53:56 +08:00
|
|
|
#ifdef BSP_USING_UART3
|
|
|
|
uart_obj[UART3_INDEX].uart_dma_flag = 0;
|
|
|
|
#ifdef BSP_UART3_RX_USING_DMA
|
|
|
|
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
|
|
|
|
static struct hc32_uart_rxto uart3_rx_timeout = UART3_RXTO_CONFIG;
|
|
|
|
uart3_dma_rx.irq_callback = hc32_uart3_dma_rx_irq_handler;
|
|
|
|
uart3_rx_timeout.irq_callback = hc32_uart3_rxto_irq_handler;
|
|
|
|
uart_config[UART3_INDEX].rx_timeout = &uart3_rx_timeout;
|
|
|
|
uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_UART3_TX_USING_DMA
|
|
|
|
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
|
|
|
|
uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
|
|
|
|
static struct hc32_uart_irq_config uart3_tc_irq = UART3_TX_CPLT_CONFIG;
|
|
|
|
uart3_tc_irq.irq_callback = hc32_uart3_tc_irq_handler;
|
|
|
|
uart_config[UART3_INDEX].tc_irq = &uart3_tc_irq;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef BSP_USING_UART4
|
|
|
|
uart_obj[UART4_INDEX].uart_dma_flag = 0;
|
|
|
|
#ifdef BSP_UART4_RX_USING_DMA
|
|
|
|
uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
|
|
|
|
static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
|
|
|
|
uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
|
|
|
|
uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
|
|
|
|
uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
|
|
|
|
uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_UART4_TX_USING_DMA
|
|
|
|
uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
|
|
|
|
uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
|
|
|
|
static struct hc32_uart_irq_config uart4_tc_irq = UART4_TX_CPLT_CONFIG;
|
|
|
|
uart4_tc_irq.irq_callback = hc32_uart4_tc_irq_handler;
|
|
|
|
uart_config[UART4_INDEX].tc_irq = &uart4_tc_irq;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2022-05-06 09:28:21 +08:00
|
|
|
#ifdef BSP_USING_UART6
|
|
|
|
uart_obj[UART6_INDEX].uart_dma_flag = 0;
|
|
|
|
#ifdef BSP_UART6_RX_USING_DMA
|
|
|
|
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
|
|
|
|
static struct hc32_uart_rxto uart6_rx_timeout = UART6_RXTO_CONFIG;
|
|
|
|
uart6_dma_rx.irq_callback = hc32_uart6_dma_rx_irq_handler;
|
|
|
|
uart6_rx_timeout.irq_callback = hc32_uart6_rxto_irq_handler;
|
|
|
|
uart_config[UART6_INDEX].rx_timeout = &uart6_rx_timeout;
|
|
|
|
uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_UART6_TX_USING_DMA
|
|
|
|
uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
static struct dma_config uart6_dma_tx = UART6_DMA_TX_CONFIG;
|
|
|
|
uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
|
|
|
|
static struct hc32_uart_irq_config uart6_tc_irq = UART6_TX_CPLT_CONFIG;
|
|
|
|
uart6_tc_irq.irq_callback = hc32_uart6_tc_irq_handler;
|
|
|
|
uart_config[UART6_INDEX].tc_irq = &uart6_tc_irq;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef BSP_USING_UART7
|
|
|
|
uart_obj[UART7_INDEX].uart_dma_flag = 0;
|
|
|
|
#ifdef BSP_UART7_RX_USING_DMA
|
|
|
|
uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
|
|
|
|
static struct hc32_uart_rxto uart7_rx_timeout = UART7_RXTO_CONFIG;
|
|
|
|
uart7_dma_rx.irq_callback = hc32_uart7_dma_rx_irq_handler;
|
|
|
|
uart7_rx_timeout.irq_callback = hc32_uart7_rxto_irq_handler;
|
|
|
|
uart_config[UART7_INDEX].rx_timeout = &uart7_rx_timeout;
|
|
|
|
uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_UART7_TX_USING_DMA
|
|
|
|
uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
static struct dma_config uart7_dma_tx = UART7_DMA_TX_CONFIG;
|
|
|
|
uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
|
|
|
|
static struct hc32_uart_irq_config uart7_tc_irq = UART7_TX_CPLT_CONFIG;
|
|
|
|
uart7_tc_irq.irq_callback = hc32_uart7_tc_irq_handler;
|
|
|
|
uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief This function gets uart irq handle.
|
|
|
|
* @param None
|
|
|
|
* @retval None
|
|
|
|
*/
|
|
|
|
static void hc32_get_uart_callback(void)
|
|
|
|
{
|
|
|
|
#ifdef BSP_USING_UART1
|
|
|
|
uart_config[UART1_INDEX].rxerr_irq.irq_callback = hc32_uart1_rxerr_irq_handler;
|
|
|
|
uart_config[UART1_INDEX].rx_irq.irq_callback = hc32_uart1_rx_irq_handler;
|
|
|
|
uart_config[UART1_INDEX].tx_irq.irq_callback = hc32_uart1_tx_irq_handler;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART2
|
|
|
|
uart_config[UART2_INDEX].rxerr_irq.irq_callback = hc32_uart2_rxerr_irq_handler;
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uart_config[UART2_INDEX].rx_irq.irq_callback = hc32_uart2_rx_irq_handler;
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uart_config[UART2_INDEX].tx_irq.irq_callback = hc32_uart2_tx_irq_handler;
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#endif
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#ifdef BSP_USING_UART3
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uart_config[UART3_INDEX].rxerr_irq.irq_callback = hc32_uart3_rxerr_irq_handler;
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uart_config[UART3_INDEX].rx_irq.irq_callback = hc32_uart3_rx_irq_handler;
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uart_config[UART3_INDEX].tx_irq.irq_callback = hc32_uart3_tx_irq_handler;
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#endif
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#ifdef BSP_USING_UART4
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uart_config[UART4_INDEX].rxerr_irq.irq_callback = hc32_uart4_rxerr_irq_handler;
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uart_config[UART4_INDEX].rx_irq.irq_callback = hc32_uart4_rx_irq_handler;
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uart_config[UART4_INDEX].tx_irq.irq_callback = hc32_uart4_tx_irq_handler;
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#endif
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#ifdef BSP_USING_UART5
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uart_config[UART5_INDEX].rxerr_irq.irq_callback = hc32_uart5_rxerr_irq_handler;
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uart_config[UART5_INDEX].rx_irq.irq_callback = hc32_uart5_rx_irq_handler;
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uart_config[UART5_INDEX].tx_irq.irq_callback = hc32_uart5_tx_irq_handler;
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#endif
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#ifdef BSP_USING_UART6
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uart_config[UART6_INDEX].rxerr_irq.irq_callback = hc32_uart6_rxerr_irq_handler;
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uart_config[UART6_INDEX].rx_irq.irq_callback = hc32_uart6_rx_irq_handler;
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|
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uart_config[UART6_INDEX].tx_irq.irq_callback = hc32_uart6_tx_irq_handler;
|
|
|
|
#endif
|
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|
|
#ifdef BSP_USING_UART7
|
|
|
|
uart_config[UART7_INDEX].rxerr_irq.irq_callback = hc32_uart7_rxerr_irq_handler;
|
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|
|
uart_config[UART7_INDEX].rx_irq.irq_callback = hc32_uart7_rx_irq_handler;
|
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|
|
uart_config[UART7_INDEX].tx_irq.irq_callback = hc32_uart7_tx_irq_handler;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART8
|
|
|
|
uart_config[UART8_INDEX].rxerr_irq.irq_callback = hc32_uart8_rxerr_irq_handler;
|
|
|
|
uart_config[UART8_INDEX].rx_irq.irq_callback = hc32_uart8_rx_irq_handler;
|
|
|
|
uart_config[UART8_INDEX].tx_irq.irq_callback = hc32_uart8_tx_irq_handler;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART9
|
|
|
|
uart_config[UART9_INDEX].rxerr_irq.irq_callback = hc32_uart9_rxerr_irq_handler;
|
|
|
|
uart_config[UART9_INDEX].rx_irq.irq_callback = hc32_uart9_rx_irq_handler;
|
|
|
|
uart_config[UART9_INDEX].tx_irq.irq_callback = hc32_uart9_tx_irq_handler;
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART10
|
|
|
|
uart_config[UART10_INDEX].rxerr_irq.irq_callback = hc32_uart10_rxerr_irq_handler;
|
|
|
|
uart_config[UART10_INDEX].rx_irq.irq_callback = hc32_uart10_rx_irq_handler;
|
|
|
|
uart_config[UART10_INDEX].tx_irq.irq_callback = hc32_uart10_tx_irq_handler;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct rt_uart_ops hc32_uart_ops =
|
|
|
|
{
|
|
|
|
.configure = hc32_configure,
|
|
|
|
.control = hc32_control,
|
|
|
|
.putc = hc32_putc,
|
|
|
|
.getc = hc32_getc,
|
|
|
|
.dma_transmit = hc32_dma_transmit
|
|
|
|
};
|
|
|
|
|
|
|
|
int hc32_hw_uart_init(void)
|
|
|
|
{
|
|
|
|
rt_err_t result = RT_EOK;
|
|
|
|
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart);
|
|
|
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
|
|
|
|
|
|
|
hc32_uart_get_dma_info();
|
|
|
|
hc32_get_uart_callback();
|
|
|
|
|
|
|
|
for (int i = 0; i < obj_num; i++)
|
|
|
|
{
|
|
|
|
/* init UART object */
|
|
|
|
uart_obj[i].serial.ops = &hc32_uart_ops;
|
|
|
|
uart_obj[i].serial.config = config;
|
|
|
|
uart_obj[i].config = &uart_config[i];
|
|
|
|
/* register the handle */
|
|
|
|
hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE);
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
|
|
|
|
{
|
|
|
|
hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE);
|
|
|
|
hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE);
|
|
|
|
}
|
|
|
|
if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
|
|
|
|
{
|
|
|
|
hc32_install_irq_handler(&uart_config[i].tc_irq->irq_config, uart_config[i].tc_irq->irq_callback, RT_FALSE);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* register UART device */
|
|
|
|
result = rt_hw_serial_register(&uart_obj[i].serial,
|
|
|
|
uart_obj[i].config->name,
|
|
|
|
(RT_DEVICE_FLAG_RDWR |
|
|
|
|
RT_DEVICE_FLAG_INT_RX |
|
|
|
|
RT_DEVICE_FLAG_INT_TX |
|
|
|
|
uart_obj[i].uart_dma_flag),
|
|
|
|
&uart_obj[i]);
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
INIT_BOARD_EXPORT(hc32_hw_uart_init);
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif /* RT_USING_SERIAL */
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* EOF (not truncated)
|
|
|
|
******************************************************************************/
|