2017-07-01 13:42:28 +08:00
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/*
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2018-10-22 11:02:14 +08:00
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* COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
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2021-04-09 10:52:34 +08:00
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*
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2018-10-22 11:02:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2021-04-09 10:52:34 +08:00
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*
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2017-07-01 13:42:28 +08:00
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* Change Logs:
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* Date Author Notes
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* 2015-07-15 Bernard The first version
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*/
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#include <board.h>
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#include <rtthread.h>
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#include "drv_emac.h"
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#if defined(RT_USING_LWIP)
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#include <finsh.h>
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#include <stdint.h>
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#include <netif/ethernetif.h>
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#include <lwip/opt.h>
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#include "MK64F12.h"
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#include "fsl_port.h"
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#include "fsl_enet.h"
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#include "fsl_phy.h"
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//#define DRV_EMAC_DEBUG
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//#define DRV_EMAC_RX_DUMP
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//#define DRV_EMAC_TX_DUMP
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#ifdef DRV_EMAC_DEBUG
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#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
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#else
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#define DEBUG_PRINTF(...)
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#endif
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2021-04-09 10:52:34 +08:00
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#define MAX_ADDR_LEN 6
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2017-07-01 13:42:28 +08:00
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#define ENET_RX_RING_LEN (16)
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#define ENET_TX_RING_LEN (8)
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#define K64_EMAC_DEVICE(eth) (struct emac_device*)(eth)
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#define ENET_ALIGN(x) \
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((unsigned int)((x) + ((ENET_BUFF_ALIGNMENT)-1)) & (unsigned int)(~(unsigned int)((ENET_BUFF_ALIGNMENT)-1)))
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#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
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#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
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#define ENET_ETH_MAX_FLEN (1522) // recommended size for a VLAN frame
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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struct emac_device
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{
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/* inherit from Ethernet device */
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struct eth_device parent;
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2021-04-09 10:52:34 +08:00
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2022-12-12 02:12:03 +08:00
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rt_align(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN];
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rt_align(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN];
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rt_align(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)];
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rt_align(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)];
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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enet_handle_t enet_handle;
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* MAC address */
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struct rt_semaphore tx_wait;
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};
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static struct emac_device _emac;
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static void setup_k64_io_enet(void)
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{
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port_pin_config_t configENET = {0};
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#ifndef FEATURE_UVISOR
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/* Disable MPU only when uVisor is not around. */
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SYSMPU->CESR &= ~SYSMPU_CESR_VLD_MASK;
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#endif/*FEATURE_UVISOR*/
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/* Affects PORTC_PCR16 register */
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PORT_SetPinMux(PORTC, 16u, kPORT_MuxAlt4);
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/* Affects PORTC_PCR17 register */
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PORT_SetPinMux(PORTC, 17u, kPORT_MuxAlt4);
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/* Affects PORTC_PCR18 register */
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PORT_SetPinMux(PORTC, 18u, kPORT_MuxAlt4);
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/* Affects PORTC_PCR19 register */
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PORT_SetPinMux(PORTC, 19u, kPORT_MuxAlt4);
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/* Affects PORTB_PCR1 register */
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PORT_SetPinMux(PORTB, 1u, kPORT_MuxAlt4);
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configENET.openDrainEnable = kPORT_OpenDrainEnable;
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configENET.mux = kPORT_MuxAlt4;
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configENET.pullSelect = kPORT_PullUp;
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/* Ungate the port clock */
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CLOCK_EnableClock(kCLOCK_PortA);
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/* Affects PORTB_PCR0 register */
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PORT_SetPinConfig(PORTB, 0u, &configENET);
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/* Affects PORTA_PCR13 register */
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PORT_SetPinMux(PORTA, 13u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR12 register */
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PORT_SetPinMux(PORTA, 12u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR14 register */
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PORT_SetPinMux(PORTA, 14u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR5 register */
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PORT_SetPinMux(PORTA, 5u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR16 register */
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PORT_SetPinMux(PORTA, 16u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR17 register */
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PORT_SetPinMux(PORTA, 17u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR15 register */
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PORT_SetPinMux(PORTA, 15u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR28 register */
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PORT_SetPinMux(PORTA, 28u, kPORT_MuxAlt4);
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}
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static void setup_enet_clock_init(void)
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{
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CLOCK_EnableClock(kCLOCK_PortC);
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CLOCK_EnableClock(kCLOCK_PortB);
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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/* Select the Ethernet timestamp clock source */
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CLOCK_SetEnetTime0Clock(0x2);
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}
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static void enet_mac_rx_isr(struct emac_device* emac)
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{
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rt_err_t result;
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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result = eth_device_ready(&(_emac.parent));
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if( result != RT_EOK )
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{
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DEBUG_PRINTF("RX err =%d\n", result );
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}
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}
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static void enet_mac_tx_isr(struct emac_device* emac)
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{
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rt_sem_release(&emac->tx_wait);
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}
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static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param)
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{
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struct emac_device* emac = param;
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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switch (event)
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{
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case kENET_RxEvent:
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enet_mac_rx_isr(emac);
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break;
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case kENET_TxEvent:
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enet_mac_tx_isr(emac);
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break;
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default:
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break;
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}
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}
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static rt_err_t k64_emac_init(rt_device_t dev)
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{
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struct emac_device* emac = K64_EMAC_DEVICE(dev);
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enet_handle_t * enet_handle = &emac->enet_handle;
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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bool link = false;
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uint32_t phyAddr = 0;
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phy_speed_t phy_speed;
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phy_duplex_t phy_duplex;
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uint32_t sysClock;
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enet_buffer_config_t buffCfg;
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enet_config_t config;
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/* initialize config according to emac device */
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setup_enet_clock_init();
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/* enable iomux and clock */
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setup_k64_io_enet();
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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/* prepare the buffer configuration. */
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buffCfg.rxBdNumber = ENET_RX_RING_LEN; /* Receive buffer descriptor number. */
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buffCfg.txBdNumber = ENET_TX_RING_LEN; /* Transmit buffer descriptor number. */
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buffCfg.rxBuffSizeAlign = ENET_ALIGN(ENET_RXBUFF_SIZE); /* Aligned receive data buffer size. */
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buffCfg.txBuffSizeAlign = ENET_ALIGN(ENET_TXBUFF_SIZE); /* Aligned transmit data buffer size. */
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buffCfg.rxBdStartAddrAlign = emac->RxBuffDescrip; /* Aligned receive buffer descriptor start address. */
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buffCfg.txBdStartAddrAlign = emac->TxBuffDescrip; /* Aligned transmit buffer descriptor start address. */
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buffCfg.rxBufferAlign = emac->RxDataBuff; /* Receive data buffer start address. */
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buffCfg.txBufferAlign = emac->TxDataBuff; /* Transmit data buffer start address. */
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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sysClock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
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DEBUG_PRINTF("sysClock: %d\n", sysClock);
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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ENET_GetDefaultConfig(&config);
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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PHY_Init(ENET, 0, CLOCK_GetFreq(kCLOCK_CoreSysClk));
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if (PHY_GetLinkStatus(ENET, phyAddr, &link) == kStatus_Success)
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{
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if (link)
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{
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DEBUG_PRINTF("phy link up\n");
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/* Get link information from PHY */
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PHY_GetLinkSpeedDuplex(ENET, phyAddr, &phy_speed, &phy_duplex);
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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/* Change the MII speed and duplex for actual link status. */
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config.miiSpeed = (enet_mii_speed_t)phy_speed;
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config.miiDuplex = (enet_mii_duplex_t)phy_duplex;
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config.interrupt = kENET_RxFrameInterrupt | kENET_TxFrameInterrupt;
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}
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else
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{
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DEBUG_PRINTF("phy link down\n");
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}
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config.rxMaxFrameLen = ENET_ETH_MAX_FLEN;
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config.macSpecialConfig = kENET_ControlFlowControlEnable;
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config.txAccelerConfig = 0;
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config.rxAccelerConfig = kENET_RxAccelMacCheckEnabled;
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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ENET_Init(ENET, enet_handle, &config, &buffCfg, emac->dev_addr, sysClock);
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ENET_SetCallback(enet_handle, ethernet_callback, emac);
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ENET_ActiveRead(ENET);
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}
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else
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{
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DEBUG_PRINTF("read phy failed\n");
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}
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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return RT_EOK;
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}
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static rt_err_t k64_emac_open(rt_device_t dev, rt_uint16_t oflag)
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{
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return RT_EOK;
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}
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static rt_err_t k64_emac_close(rt_device_t dev)
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{
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return RT_EOK;
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}
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static rt_size_t k64_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t k64_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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2017-10-16 13:23:03 +08:00
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static rt_err_t k64_emac_control(rt_device_t dev, int cmd, void *args)
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2017-07-01 13:42:28 +08:00
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{
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struct emac_device *emac;
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2021-04-09 10:52:34 +08:00
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DEBUG_PRINTF("k64_emac_control\n");
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2017-07-01 13:42:28 +08:00
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emac = K64_EMAC_DEVICE(dev);
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RT_ASSERT(emac != RT_NULL);
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switch(cmd)
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{
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case NIOCTL_GADDR:
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/* get MAC address */
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if(args) rt_memcpy(args, emac->dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p)
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{
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rt_err_t result = RT_EOK;
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struct emac_device *emac = K64_EMAC_DEVICE(dev);
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enet_handle_t * enet_handle = &emac->enet_handle;
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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RT_ASSERT(p != NULL);
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2021-04-09 10:52:34 +08:00
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DEBUG_PRINTF("k64_emac_tx: %d\n", p->len);
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2017-07-01 13:42:28 +08:00
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emac = K64_EMAC_DEVICE(dev);
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RT_ASSERT(emac != RT_NULL);
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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#ifdef DRV_EMAC_RX_DUMP
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{
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int i;
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uint8_t * buf;
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buf = (uint8_t *)p->payload;
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for (i = 0; i < p->len; i++)
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{
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DEBUG_PRINTF("%02X ", buf[i]);
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if (i % 16 == 15)
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DEBUG_PRINTF("\n");
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}
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DEBUG_PRINTF("\n");
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2021-04-09 10:52:34 +08:00
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}
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2017-07-01 13:42:28 +08:00
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#endif
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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do
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{
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result = ENET_SendFrame(ENET, enet_handle, p->payload, p->len);
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if (result == kStatus_ENET_TxFrameBusy)
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{
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rt_sem_take(&emac->tx_wait, RT_WAITING_FOREVER);
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}
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} while (result == kStatus_ENET_TxFrameBusy);
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return RT_EOK;
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}
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struct pbuf *k64_emac_rx(rt_device_t dev)
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{
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uint32_t length = 0;
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status_t status;
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enet_data_error_stats_t eErrStatic;
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2021-04-09 10:52:34 +08:00
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2017-07-01 13:42:28 +08:00
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struct pbuf* p = RT_NULL;
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struct emac_device *emac = K64_EMAC_DEVICE(dev);
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enet_handle_t * enet_handle = &emac->enet_handle;
|
|
|
|
|
|
|
|
RT_ASSERT(emac != RT_NULL);
|
|
|
|
DEBUG_PRINTF("k64_emac_rx\n");
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
/* Get the Frame size */
|
|
|
|
status = ENET_GetRxFrameSize(enet_handle, &length);
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
if (status == kStatus_ENET_RxFrameError)
|
|
|
|
{
|
|
|
|
/* Update the received buffer when error happened. */
|
|
|
|
/* Get the error information of the received g_frame. */
|
|
|
|
ENET_GetRxErrBeforeReadFrame(enet_handle, &eErrStatic);
|
|
|
|
/* update the receive buffer. */
|
|
|
|
ENET_ReadFrame(ENET, enet_handle, NULL, 0);
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
DEBUG_PRINTF("receive frame faild\n");
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
return p;
|
|
|
|
}
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
/* Call ENET_ReadFrame when there is a received frame. */
|
|
|
|
if (length != 0)
|
|
|
|
{
|
|
|
|
/* Received valid frame. Deliver the rx buffer with the size equal to length. */
|
|
|
|
p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
|
|
|
|
}
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
if (p != NULL)
|
|
|
|
{
|
|
|
|
status = ENET_ReadFrame(ENET, enet_handle, p->payload, length);
|
|
|
|
if (status == kStatus_Success)
|
|
|
|
{
|
|
|
|
#ifdef DRV_EMAC_RX_DUMP
|
|
|
|
uint8_t *buf;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DEBUG_PRINTF(" A frame received. the length:%d\n", p->len);
|
|
|
|
buf = (uint8_t *)p->payload;
|
|
|
|
for (i = 0; i < p->len; i++)
|
|
|
|
{
|
|
|
|
DEBUG_PRINTF("%02X ", buf[i]);
|
|
|
|
if (i % 16 == 15)
|
|
|
|
DEBUG_PRINTF("\n");
|
|
|
|
}
|
|
|
|
DEBUG_PRINTF("\n");
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
DEBUG_PRINTF(" A frame read failed\n");
|
|
|
|
pbuf_free(p);
|
|
|
|
}
|
|
|
|
}
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
return p;
|
|
|
|
}
|
|
|
|
|
|
|
|
int drv_emac_hw_init(void)
|
|
|
|
{
|
|
|
|
/* use the test MAC address */
|
|
|
|
_emac.dev_addr[0] = 0x00;
|
|
|
|
_emac.dev_addr[1] = 0x04;
|
|
|
|
_emac.dev_addr[2] = 0x9f;
|
|
|
|
_emac.dev_addr[3] = 0xc4;
|
|
|
|
_emac.dev_addr[4] = 0x44;
|
|
|
|
_emac.dev_addr[5] = 0x22;
|
|
|
|
|
|
|
|
_emac.parent.parent.init = k64_emac_init;
|
|
|
|
_emac.parent.parent.open = k64_emac_open;
|
|
|
|
_emac.parent.parent.close = k64_emac_close;
|
|
|
|
_emac.parent.parent.read = k64_emac_read;
|
|
|
|
_emac.parent.parent.write = k64_emac_write;
|
|
|
|
_emac.parent.parent.control = k64_emac_control;
|
|
|
|
_emac.parent.parent.user_data = RT_NULL;
|
|
|
|
|
|
|
|
_emac.parent.eth_rx = k64_emac_rx;
|
|
|
|
_emac.parent.eth_tx = k64_emac_tx;
|
|
|
|
|
|
|
|
/* init tx semaphore */
|
|
|
|
rt_sem_init(&_emac.tx_wait, "tx_wait", ENET_TX_RING_LEN - 1, RT_IPC_FLAG_FIFO);
|
2021-04-09 10:52:34 +08:00
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
/* register ETH device */
|
|
|
|
eth_device_init(&(_emac.parent), "e0");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(drv_emac_hw_init);
|
|
|
|
|
|
|
|
#ifdef DRV_EMAC_DEBUG
|
|
|
|
|
|
|
|
long k64_dump_tx_bd(void)
|
|
|
|
{
|
2021-04-09 10:52:34 +08:00
|
|
|
int i;
|
2017-07-01 13:42:28 +08:00
|
|
|
|
2021-04-09 10:52:34 +08:00
|
|
|
enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip;
|
|
|
|
|
|
|
|
for (i = 0; i < ENET_RX_RING_LEN; i++)
|
|
|
|
{
|
|
|
|
DEBUG_PRINTF("status: %04X, length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer);
|
|
|
|
}
|
2017-07-01 13:42:28 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
FINSH_FUNCTION_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor);
|
|
|
|
MSH_CMD_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor);
|
|
|
|
|
|
|
|
long k64_dump_rx_bd(void)
|
|
|
|
{
|
2021-04-09 10:52:34 +08:00
|
|
|
int i;
|
|
|
|
enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip;
|
|
|
|
|
|
|
|
for (i = 0; i < ENET_RX_RING_LEN; i++)
|
|
|
|
{
|
|
|
|
DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]);
|
|
|
|
//rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t));
|
|
|
|
DEBUG_PRINTF("status:%04X, length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer);
|
2017-07-01 13:42:28 +08:00
|
|
|
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
|
2021-04-09 10:52:34 +08:00
|
|
|
DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2);
|
|
|
|
DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp);
|
2017-07-01 13:42:28 +08:00
|
|
|
#endif
|
2021-04-09 10:52:34 +08:00
|
|
|
DEBUG_PRINTF("\n");
|
|
|
|
}
|
|
|
|
|
2017-07-01 13:42:28 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
FINSH_FUNCTION_EXPORT(k64_dump_rx_bd, dump all receive buffer descriptor);
|
|
|
|
MSH_CMD_EXPORT(k64_dump_rx_bd, dump all receive buffer descriptor);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif
|