256 lines
8.8 KiB
C
256 lines
8.8 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_dmic.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.dmic"
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of DMIC peripheral base address. */
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static DMIC_Type *const s_dmicBases[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_BASE_PTRS;
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/* Array of DMIC clock name. */
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static const clock_ip_name_t s_dmicClock[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_CLOCKS;
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/* Array of DMIC IRQ number. */
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static const IRQn_Type s_dmicIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_IRQS;
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/*! @brief Callback function array for DMIC(s). */
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static dmic_callback_t s_dmicCallback[FSL_FEATURE_SOC_DMIC_COUNT];
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/* Array of HWVAD IRQ number. */
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static const IRQn_Type s_dmicHwvadIRQ[FSL_FEATURE_SOC_DMIC_COUNT] = DMIC_HWVAD_IRQS;
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/*! @brief Callback function array for HWVAD(s). */
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static dmic_hwvad_callback_t s_dmicHwvadCallback[FSL_FEATURE_SOC_DMIC_COUNT];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the DMIC instance from peripheral base address.
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*
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* @param base DMIC peripheral base address.
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* @return DMIC instance.
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*/
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uint32_t DMIC_GetInstance(DMIC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_dmicBases); instance++)
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{
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if (s_dmicBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_dmicBases));
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return instance;
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}
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void DMIC_Init(DMIC_Type *base)
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{
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assert(base);
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/* Enable the clock to the register interface */
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CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]);
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/* Reset the peripheral */
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RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn);
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/* Disable DMA request*/
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base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
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base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
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/* Disable DMIC interrupt. */
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base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
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base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
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}
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void DMIC_DeInit(DMIC_Type *base)
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{
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assert(base);
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/* Disable the clock to the register interface */
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CLOCK_DisableClock(s_dmicClock[DMIC_GetInstance(base)]);
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}
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void DMIC_ConfigIO(DMIC_Type *base, dmic_io_t config)
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{
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base->IOCFG = config;
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}
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void DMIC_SetOperationMode(DMIC_Type *base, operation_mode_t mode)
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{
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if (mode == kDMIC_OperationModeInterrupt)
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{
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/* Enable DMIC interrupt. */
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base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
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base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
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}
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if (mode == kDMIC_OperationModeDma)
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{
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/* enable DMA request*/
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base->CHANNEL[0].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
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base->CHANNEL[1].FIFO_CTRL |= DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
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}
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}
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void DMIC_ConfigChannel(DMIC_Type *base,
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dmic_channel_t channel,
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stereo_side_t side,
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dmic_channel_config_t *channel_config)
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{
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base->CHANNEL[channel].DIVHFCLK = channel_config->divhfclk;
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base->CHANNEL[channel].OSR = channel_config->osr;
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base->CHANNEL[channel].GAINSHIFT = channel_config->gainshft;
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base->CHANNEL[channel].PREAC2FSCOEF = channel_config->preac2coef;
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base->CHANNEL[channel].PREAC4FSCOEF = channel_config->preac4coef;
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base->CHANNEL[channel].PHY_CTRL =
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DMIC_CHANNEL_PHY_CTRL_PHY_FALL(side) | DMIC_CHANNEL_PHY_CTRL_PHY_HALF(channel_config->sample_rate);
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base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(channel_config->dc_cut_level) |
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DMIC_CHANNEL_DC_CTRL_DCGAIN(channel_config->post_dc_gain_reduce) |
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DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(channel_config->saturate16bit);
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}
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void DMIC_CfgChannelDc(DMIC_Type *base,
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dmic_channel_t channel,
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dc_removal_t dc_cut_level,
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uint32_t post_dc_gain_reduce,
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bool saturate16bit)
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{
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base->CHANNEL[channel].DC_CTRL = DMIC_CHANNEL_DC_CTRL_DCPOLE(dc_cut_level) |
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DMIC_CHANNEL_DC_CTRL_DCGAIN(post_dc_gain_reduce) |
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DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(saturate16bit);
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}
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void DMIC_Use2fs(DMIC_Type *base, bool use2fs)
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{
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base->USE2FS = (use2fs) ? 0x1 : 0x0;
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}
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void DMIC_EnableChannnel(DMIC_Type *base, uint32_t channelmask)
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{
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base->CHANEN = channelmask;
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}
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void DMIC_FifoChannel(DMIC_Type *base, uint32_t channel, uint32_t trig_level, uint32_t enable, uint32_t resetn)
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{
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base->CHANNEL[channel].FIFO_CTRL |=
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(base->CHANNEL[channel].FIFO_CTRL & (DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK | DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)) |
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DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(trig_level) | DMIC_CHANNEL_FIFO_CTRL_ENABLE(enable) |
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DMIC_CHANNEL_FIFO_CTRL_RESETN(resetn);
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}
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void DMIC_EnableIntCallback(DMIC_Type *base, dmic_callback_t cb)
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{
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uint32_t instance;
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instance = DMIC_GetInstance(base);
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NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
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/* Save callback pointer */
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s_dmicCallback[instance] = cb;
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EnableIRQ(s_dmicIRQ[instance]);
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}
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void DMIC_DisableIntCallback(DMIC_Type *base, dmic_callback_t cb)
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{
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uint32_t instance;
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instance = DMIC_GetInstance(base);
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DisableIRQ(s_dmicIRQ[instance]);
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s_dmicCallback[instance] = NULL;
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NVIC_ClearPendingIRQ(s_dmicIRQ[instance]);
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}
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void DMIC_HwvadEnableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
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{
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uint32_t instance;
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instance = DMIC_GetInstance(base);
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NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
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/* Save callback pointer */
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s_dmicHwvadCallback[instance] = vadcb;
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EnableIRQ(s_dmicHwvadIRQ[instance]);
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}
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void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
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{
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uint32_t instance;
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instance = DMIC_GetInstance(base);
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DisableIRQ(s_dmicHwvadIRQ[instance]);
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s_dmicHwvadCallback[instance] = NULL;
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NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
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}
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/* IRQ handler functions overloading weak symbols in the startup */
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#if defined(DMIC0)
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/*DMIC0 IRQ handler */
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void DMIC0_DriverIRQHandler(void)
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{
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if (s_dmicCallback[0] != NULL)
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{
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s_dmicCallback[0]();
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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/*DMIC0 HWVAD IRQ handler */
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void HWVAD0_DriverIRQHandler(void)
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{
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if (s_dmicHwvadCallback[0] != NULL)
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{
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s_dmicHwvadCallback[0]();
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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#endif
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