213 lines
12 KiB
C
213 lines
12 KiB
C
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/*!
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\file gd32e230.h
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\brief general definitions for GD32E230
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\version 2018-06-19, V1.0.0, firmware for GD32E230
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32E230_H
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#define GD32E230_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* define GD32E230 */
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#if !defined (GD32E230)
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#define GD32E230
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#endif /* define GD32E230 */
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#if !defined (GD32E230)
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#error "Please select the target GD32E230 device used in your application (in gd32e230.h file)"
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#endif /* undefine GD32E230 tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)8000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
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#if !defined (IRC8M_VALUE)
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#define IRC8M_VALUE ((uint32_t)8000000)
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#endif /* internal 8MHz RC oscillator value */
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/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
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#if !defined (IRC8M_STARTUP_TIMEOUT)
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#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 8MHz RC oscillator startup timeout */
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/* define value of internal RC oscillator for ADC in Hz */
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#if !defined (IRC28M_VALUE)
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#define IRC28M_VALUE ((uint32_t)28000000)
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#endif /* IRC28M_VALUE */
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#if !defined (IRC48M_VALUE)
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#define IRC48M_VALUE ((uint32_t)48000000)
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#endif /* IRC48M_VALUE */
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/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
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#if !defined (IRC40K_VALUE)
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#define IRC40K_VALUE ((uint32_t)40000)
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#endif /* internal 40KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* GD32E1x0 firmware library version number V1.0 */
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#define __GD32E230_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __GD32E230_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __GD32E230_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32E230_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32E230_STDPERIPH_VERSION ((__GD32E230_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32E230_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32E230_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32E230_STDPERIPH_VERSION_RC))
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/* configuration of the Cortex-M23 processor and core peripherals */
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#define __CM23_REV 0x0100U /*!< Core revision r1p0 */
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#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
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#define __MPU_PRESENT 0U /*!< MPU is present */
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#define __VTOR_PRESENT 1U /*!< VTOR is present */
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#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* Cortex-M23 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
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HardFault_IRQn = -13, /*!< hardfault interrupt */
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SVCall_IRQn = -5, /*!< sv call interrupt */
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PendSV_IRQn = -2, /*!< pend sv interrupt */
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SysTick_IRQn = -1, /*!< system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */
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FMC_IRQn = 3, /*!< FMC interrupt */
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RCU_IRQn = 4, /*!< RCU interrupt */
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EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
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EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
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EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
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DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
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DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
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DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
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ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */
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TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */
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TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
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TIMER5_IRQn = 17, /*!< TIMER5 interrupt */
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TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
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TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
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TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
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TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
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I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
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I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
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SPI0_IRQn = 25, /*!< SPI0 interrupt */
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SPI1_IRQn = 26, /*!< SPI1 interrupt */
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USART0_IRQn = 27, /*!< USART0 interrupt */
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USART1_IRQn = 28, /*!< USART1 interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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} IRQn_Type;
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/* includes */
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#include "core_cm23.h"
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#include "system_gd32e230.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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/* bit operations */
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#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
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/* SRAM and peripheral base bit-band region */
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#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
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#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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/* advanced peripheral bus 2 memory map */
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#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
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#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
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#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
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#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
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/* advanced high performance bus 1 memory map */
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#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
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#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
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#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
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#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
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#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
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/* advanced high performance bus 2 memory map */
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#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
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/* option byte and debug memory map */
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#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
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#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */
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#include "gd32e230_libopt.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* GD32E230_H */
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