518 lines
13 KiB
C
518 lines
13 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file ck_dmac.c
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* @brief CSI Source File for DMAC Driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#include <stdbool.h>
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#include "ck_dmac.h"
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#include "csi_core.h"
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#include "drv_dmac.h"
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#include "soc.h"
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#define ERR_DMA(errno) (CSI_DRV_ERRNO_DMA_BASE | errno)
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typedef struct {
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uint32_t base;
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uint32_t irq;
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dma_event_cb_t cb_event;
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uint8_t ch_num;
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} ck_dma_priv_t;
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static ck_dma_priv_t dma_instance[CONFIG_DMAC_NUM];
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static const dma_capabilities_t dma_capabilities = {
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.unalign_addr = 1, ///< support for unalign address transfer when memory is source
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};
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static volatile dma_status_e status[CK_DMA_MAXCHANNEL] = {DMA_STATE_FREE, DMA_STATE_FREE};
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static volatile uint8_t ch_opened[CK_DMA_MAXCHANNEL] = {0, 0};
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static int32_t ck_dma_set_channel(ck_dma_reg_t *addr, uint32_t source, uint32_t dest, uint32_t size)
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{
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uint32_t temp = addr->CHCTRLA;
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temp &= 0xff000fff;
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temp |= (size << 12);
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addr->SAR = source;
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addr->DAR = dest ;
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addr->CHCTRLA = temp;
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return 0;
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}
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static int32_t ck_dma_set_transfertype(ck_dma_reg_t *addr, dma_trans_type_e transtype)
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{
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uint32_t temp = addr->CHCTRLB;
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temp &= 0xffffff7f;
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if (transtype >= DMA_PERH2PERH) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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if (transtype == DMA_MEM2MEM) {
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temp |= (transtype << 7);
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} else {
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temp |= (1 << 7);
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}
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addr->CHCTRLB = temp;
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return 0;
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}
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static int32_t ck_dma_set_addrinc(ck_dma_reg_t *addr, enum_addr_state_e src_addrinc, enum_addr_state_e dst_addrinc)
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{
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if ((src_addrinc != DMA_ADDR_INCREMENT && src_addrinc != DMA_ADDR_DECREMENT && src_addrinc != DMA_ADDR_NOCHANGE) ||
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(dst_addrinc != DMA_ADDR_INCREMENT && dst_addrinc != DMA_ADDR_DECREMENT && dst_addrinc != DMA_ADDR_NOCHANGE)) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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uint32_t temp = addr->CHCTRLA;
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temp &= 0xffffff0f;
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temp |= (src_addrinc << 6);
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temp |= (dst_addrinc << 4);
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addr->CHCTRLA = temp;
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return 0;
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}
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static int32_t ck_dma_set_transferwidth(ck_dma_reg_t *addr, dma_datawidth_e src_width, dma_datawidth_e dst_width)
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{
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if ((src_width != DMA_DATAWIDTH_SIZE8 && src_width != DMA_DATAWIDTH_SIZE16 && src_width != DMA_DATAWIDTH_SIZE32) ||
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(dst_width != DMA_DATAWIDTH_SIZE8 && dst_width != DMA_DATAWIDTH_SIZE16 && dst_width != DMA_DATAWIDTH_SIZE32)) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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uint32_t temp = addr->CHCTRLA;
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temp &= 0xfffffff0;
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temp |= (src_width - 1) << 2;
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temp |= dst_width - 1;
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addr->CHCTRLA = temp;
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return 0;
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}
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static int32_t ck_dma_set_burstlength(ck_dma_reg_t *addr, uint8_t burstlength)
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{
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uint32_t temp = addr->CHCTRLA;
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temp &= 0xfffff0ff;
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temp |= (burstlength << 8);
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addr->CHCTRLA = temp;
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return 0;
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}
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/**
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\brief Set software or hardware handshaking.
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\param[in] addr pointer to dma register.
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\return error code
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*/
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static int32_t ck_dma_set_handshaking(ck_dma_reg_t *addr, dma_handshaking_select_e handshaking)
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{
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uint32_t temp = addr->CHCTRLB;
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temp &= 0xfffffeff;
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temp |= (handshaking << 8);
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addr->CHCTRLB = temp;
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return 0;
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}
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static int ck_dma_assign_hdhs_interface(ck_dma_reg_t *addr, ckenum_dma_device_e device)
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{
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if (device < 0 || device >= CKENUM_DMA_MEMORY) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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addr->CHCTRLB &= 0xffffe1ff;
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addr->CHCTRLB |= (device << 9);
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return 0;
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}
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void ck_dma_irqhandler(int32_t idx)
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{
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ck_dma_priv_t *dma_priv = &dma_instance[idx];
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ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base);
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/*
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* StatusInt_temp contain the information that which types of interrupr are
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* requested.
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*/
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int32_t count = 0;
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uint32_t temp = 0;
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for (count = 0; count < dma_priv->ch_num; count++) {
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addr = (ck_dma_reg_t *)(dma_priv->base + count * 0x30);
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temp = addr->CHINTS;
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if (temp != 0) {
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break;
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}
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}
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/* If Tfr interrupt is requested */
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if (temp == CK_DMA_TFR) {
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status[count] = DMA_STATE_DONE;
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addr->CHINTC = temp;
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if (dma_priv->cb_event) {
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dma_priv->cb_event(DMA_EVENT_TRANSFER_DONE, count);
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}
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}
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/* If Err interrput is requested */
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if (temp == CK_DMA_ERR) {
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status[count] = DMA_STATE_ERROR;
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addr->CHINTC = temp;
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if (dma_priv->cb_event) {
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dma_priv->cb_event(DMA_EVENT_TRANSFER_ERROR, count);
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}
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}
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}
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int32_t __attribute__((weak)) target_get_dmac_count(void)
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{
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return 0;
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}
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int32_t __attribute__((weak)) target_get_dmac(uint32_t idx, uint32_t *base, uint32_t *irq)
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{
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return NULL;
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}
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/**
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\brief get dma instance count.
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\return dma instance count
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*/
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int32_t csi_dma_get_instance_count(void)
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{
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return target_get_dmac_count();
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}
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/**
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\brief Initialize DMA Interface. 1. Initializes the resources needed for the DMA interface 2.registers event callback function
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\param[in] idx must not exceed return value of csi_dma_get_instance_count()
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\return pointer to dma instances
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*/
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dmac_handle_t csi_dma_initialize(int32_t idx)
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{
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if (idx < 0 || idx >= CONFIG_DMAC_NUM) {
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return NULL;
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}
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uint32_t base = 0u;
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uint32_t irq = 0u;
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int32_t real_idx = target_get_dmac(idx, &base, &irq);
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if (real_idx != idx) {
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return NULL;
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}
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ck_dma_priv_t *dma_priv = &dma_instance[idx];
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dma_priv->base = base;
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dma_priv->irq = irq;
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dma_priv->ch_num = CK_DMA_MAXCHANNEL;
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drv_nvic_enable_irq(dma_priv->irq);
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uint8_t count = 0u;
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for (count = 0; count < dma_priv->ch_num; count++) {
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ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + count * 0x30);
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addr->CHINTM = CK_DMA_MASK;
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addr->CHINTC = CK_DMA_INTC;
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}
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return (dmac_handle_t)dma_priv;
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}
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/**
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\brief De-initialize DMA Interface. stops operation and releases the software resources used by the interface
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\param[in] handle damc handle to operate.
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\return error code
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*/
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int32_t csi_dma_uninitialize(dmac_handle_t handle)
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{
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if (handle == NULL) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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ck_dma_priv_t *dma_priv = handle;
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ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base);
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uint8_t count;
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for (count = 0; count < dma_priv->ch_num; count++) {
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addr = (ck_dma_reg_t *)(dma_priv->base + count * 0x30);
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addr->CHINTM = CK_DMA_MASK;
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addr->CHINTC = CK_DMA_INTC;
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}
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drv_nvic_disable_irq(dma_priv->irq);
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return 0;
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}
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/**
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\brief Get driver capabilities.
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\param[in] handle damc handle to operate.
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\return \ref dma_capabilities_t
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*/
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dma_capabilities_t csi_dma_get_capabilities(dmac_handle_t handle)
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{
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return dma_capabilities;
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}
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/**
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\brief get one free dma channel
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\param[in] handle damc handle to operate.
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\param[in] ch channel num. if -1 then allocate a free channal in this dma
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\return -1 - no channel can be used, other - channel index
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*/
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int32_t csi_dma_alloc_channel(dmac_handle_t handle, int32_t ch)
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{
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ck_dma_priv_t *dma_priv = handle;
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if (handle == NULL || ch > dma_priv->ch_num) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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uint8_t ch_num = 0;
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ck_dma_reg_t *addr = NULL;
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if (ch == -1) { // alloc a free channal
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for (ch_num = 0; ch_num < dma_priv->ch_num; ch_num++) {
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addr = (ck_dma_reg_t *)(dma_priv->base + ch_num * 0x30);
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if (ch_opened[ch_num] != 0x1) {
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ch_opened[ch_num] = 1;
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break;
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}
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}
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if (ch_num >= dma_priv->ch_num) {
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return -1;
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}
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} else { //alloc a fixed channel
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addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
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if (ch_opened[ch] == 0x1) {
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return ERR_DMA(EDRV_BUSY);
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}
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ch_opened[ch] = 1;
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ch_num = ch;
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}
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addr->CHINTC = CK_DMA_INTC;
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addr->CHINTM &= ~CK_DMA_MASK;
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status[ch_num] = DMA_STATE_READY;
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return ch_num;
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}
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/**
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\brief release dma channel and related resources
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\param[in] handle damc handle to operate.
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\param[in] ch channel num.
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\return error code
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*/
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int32_t csi_dma_release_channel(dmac_handle_t handle, int32_t ch)
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{
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ck_dma_priv_t *dma_priv = handle;
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if (handle == NULL || ch >= dma_priv->ch_num || ch < 0) {
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return ERR_DMA(EDRV_PARAMETER);
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}
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ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
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status[ch] = DMA_STATE_FREE;
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ch_opened[ch] = 0;
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addr->CHINTC = CK_DMA_INTC;
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addr->CHINTM = CK_DMA_MASK;
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return 0;
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}
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/**
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\brief
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\param[in] handle damc handle to operate.
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\param[in] ch channel num. if -1 then allocate a free channal in this dma
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\param[in] psrcaddr dma transfer source address
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\param[in] pstdaddr dma transfer source address
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\param[in] length dma transfer length
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\param[in] config dma transfer configure
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\param[in] cb_event Pointer to \ref dma_event_cb_t
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\return error code
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*/
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int32_t csi_dma_config(dmac_handle_t handle, int32_t ch,
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void *psrcaddr, void *pstdaddr,
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uint32_t length, dma_config_t *config, dma_event_cb_t cb_event)
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{
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ck_dma_priv_t *dma_priv = handle;
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|
|
||
|
|
if (handle == NULL || ch >= dma_priv->ch_num || config == NULL) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ch == -1) { //alloc a free channel
|
||
|
|
ch = csi_dma_alloc_channel(handle, -1);
|
||
|
|
|
||
|
|
if (ch < 0) {
|
||
|
|
return ERR_DMA(EDRV_BUSY);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
dma_priv->cb_event = cb_event;
|
||
|
|
|
||
|
|
ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
|
||
|
|
|
||
|
|
/* Initializes corresponding channel registers */
|
||
|
|
|
||
|
|
if ((length * config->src_tw) % config->dst_tw != 0) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t ret = ck_dma_set_transferwidth(addr, config->src_tw, config->dst_tw);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t grouplen = ((length * config->src_tw / config->dst_tw) - 1) % 16;
|
||
|
|
ck_dma_set_burstlength(addr, grouplen);
|
||
|
|
|
||
|
|
ret = ck_dma_set_transfertype(addr, config->type);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config->type == DMA_MEM2MEM) {
|
||
|
|
ck_dma_set_handshaking(addr, DMA_HANDSHAKING_SOFTWARE);
|
||
|
|
ret = ck_dma_set_addrinc(addr , config->src_inc, config->dst_inc);
|
||
|
|
} else if (config->type == DMA_MEM2PERH) {
|
||
|
|
ck_dma_set_handshaking(addr, DMA_HANDSHAKING_HARDWARE);
|
||
|
|
ret = ck_dma_set_addrinc(addr , config->src_inc, config->dst_inc);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = ck_dma_assign_hdhs_interface(addr, config->hs_if);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
} else if (config->type == DMA_PERH2MEM) {
|
||
|
|
ck_dma_set_handshaking(addr, DMA_HANDSHAKING_HARDWARE);
|
||
|
|
ret = ck_dma_set_addrinc(addr , config->src_inc, config->dst_inc);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = ck_dma_assign_hdhs_interface(addr, config->hs_if);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
ck_dma_set_channel(addr, (uint32_t)psrcaddr, (uint32_t)pstdaddr, length);
|
||
|
|
status[ch] = DMA_STATE_READY;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief start generate dma signal.
|
||
|
|
\param[in] handle damc handle to operate.
|
||
|
|
\param[in] ch channel num.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_dma_start(dmac_handle_t handle, int32_t ch)
|
||
|
|
{
|
||
|
|
ck_dma_priv_t *dma_priv = handle;
|
||
|
|
|
||
|
|
if (handle == NULL || ch >= dma_priv->ch_num || ch < 0) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
status[ch] = DMA_STATE_BUSY;
|
||
|
|
ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
|
||
|
|
addr->CHCTRLB |= CK_DMA_INT_EN; // interrupt enable
|
||
|
|
addr->CHEN |= CK_DMA_CH_EN;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Stop generate dma signal.
|
||
|
|
\param[in] handle damc handle to operate.
|
||
|
|
\param[in] ch channel num.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_dma_stop(dmac_handle_t handle, int32_t ch)
|
||
|
|
{
|
||
|
|
if (handle == NULL) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
ck_dma_priv_t *dma_priv = handle;
|
||
|
|
|
||
|
|
if (ch >= dma_priv->ch_num || ch < 0) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
status[ch] = DMA_STATE_DONE;
|
||
|
|
|
||
|
|
ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
|
||
|
|
addr->CHCTRLB &= ~CK_DMA_INT_EN; // interrupt disable
|
||
|
|
addr->CHEN &= ~CK_DMA_CH_EN;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get DMA status.
|
||
|
|
\param[in] handle damc handle to operate.
|
||
|
|
\param[in] ch channel num.
|
||
|
|
\return DMA status \ref dma_status_t
|
||
|
|
*/
|
||
|
|
dma_status_e csi_dma_get_status(dmac_handle_t handle, int32_t ch)
|
||
|
|
{
|
||
|
|
if (handle == NULL) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
ck_dma_priv_t *dma_priv = handle;
|
||
|
|
|
||
|
|
if (ch >= dma_priv->ch_num || ch < 0) {
|
||
|
|
return ERR_DMA(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
return status[ch];
|
||
|
|
}
|
||
|
|
|