134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
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/*
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* File : interrupt.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first version
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*/
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#include <rtthread.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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/* interrupt nest */
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extern volatile rt_uint8_t rt_interrupt_nest;
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/* exception and interrupt handler table */
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#define MAX_HANDLERS 32
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rt_isr_handler_t isr_table[MAX_HANDLERS];
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrput_flag;
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rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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return RT_NULL;
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}
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void uic_irq_ack(unsigned int vec)
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{
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mtdcr(uic0sr, UIC_MASK(vec));
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}
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void uic_int_handler (unsigned int vec)
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{
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rt_interrupt_enter();
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/* Allow external interrupts to the CPU. */
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if (isr_table [vec] != 0)
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{
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(*isr_table[vec])(vec);
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}
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uic_irq_ack(vec);
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rt_interrupt_leave();
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}
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/* handler for UIC interrupt */
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void uic_interrupt(rt_uint32_t uic_base, int vec_base)
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{
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int vec;
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rt_uint32_t uic_msr;
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rt_uint32_t msr_shift;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = get_dcr(uic_base + UIC_MSR);
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msr_shift = uic_msr;
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vec = vec_base;
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while (msr_shift != 0)
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{
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if (msr_shift & 0x80000000)
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uic_int_handler(vec);
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
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{
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int intVal;
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if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS))
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{
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return; /* out of range */
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}
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/* install the handler in the system interrupt table */
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intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */
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if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
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if (new_handler != RT_NULL) isr_table[vector] = new_handler;
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rt_hw_interrupt_enable (intVal);
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}
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void rt_hw_interrupt_mask(int vector)
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{
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mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
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}
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void rt_hw_interrupt_unmask(int vector)
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{
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mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
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}
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void rt_hw_interrupt_init()
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{
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int vector;
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rt_uint32_t pit_value;
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pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ);
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/* enable pit */
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mtspr(SPRN_PIT, pit_value);
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mtspr(SPRN_TCR, 0x4400000);
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/* set default interrupt handler */
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for (vector = 0; vector < MAX_HANDLERS; vector++)
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{
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isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle;
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}
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/* initialize interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrput_flag = 0;
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}
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/*@}*/
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