2016-04-18 13:52:39 +08:00
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef FH_I2C_H_
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#define FH_I2C_H_
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#include "fh_def.h"
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#define OFFSET_I2C_CON (0x0000)
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#define OFFSET_I2C_TAR (0x0004)
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#define OFFSET_I2C_SAR (0x0008)
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#define OFFSET_I2C_HS_MADDR (0x000C)
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#define OFFSET_I2C_DATA_CMD (0x0010)
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#define OFFSET_I2C_SS_SCL_HCNT (0x0014)
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#define OFFSET_I2C_SS_SCL_LCNT (0x0018)
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#define OFFSET_I2C_FS_SCL_HCNT (0x001C)
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#define OFFSET_I2C_FS_SCL_LCNT (0x0020)
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#define OFFSET_I2C_HS_SCL_HCNT (0x0024)
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#define OFFSET_I2C_HS_SCL_LCNT (0x0028)
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#define OFFSET_I2C_INTR_STAT (0x002c)
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#define OFFSET_I2C_INTR_MASK (0x0030)
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#define OFFSET_I2C_RAW_INTR_STAT (0x0034)
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#define OFFSET_I2C_RX_TL (0x0038)
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#define OFFSET_I2C_TX_TL (0x003c)
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#define OFFSET_I2C_CLR_INTR (0x0040)
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#define OFFSET_I2C_CLR_RX_UNDER (0x0044)
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#define OFFSET_I2C_CLR_RX_OVER (0x0048)
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#define OFFSET_I2C_CLR_TX_OVER (0x004c)
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#define OFFSET_I2C_CLR_RD_REQ (0x0050)
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#define OFFSET_I2C_CLR_TX_ABRT (0x0054)
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#define OFFSET_I2C_CLR_RX_DONE (0x0058)
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#define OFFSET_I2C_CLR_ACTIVITY (0x005c)
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#define OFFSET_I2C_CLR_STOP_DET (0x0060)
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#define OFFSET_I2C_CLR_START_DET (0x0064)
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#define OFFSET_I2C_CLR_GEN_CALL (0x0068)
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#define OFFSET_I2C_ENABLE (0x006c)
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#define OFFSET_I2C_STATUS (0x0070)
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#define OFFSET_I2C_TXFLR (0x0074)
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#define OFFSET_I2C_RXFLR (0x0078)
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#define OFFSET_I2C_DMA_CR (0x0088)
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#define OFFSET_I2C_DMA_TDLR (0x008c)
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#define OFFSET_I2C_DMA_RDLR (0x0090)
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#define OFFSET_I2C_COMP_PARAM1 (0x00f4)
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#define OFFSET_I2C_TX_ABRT_SOURCE (0x0080)
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#define I2C_M_TEN 0x0100 /* this is a ten bit chip address */
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#define I2C_M_RD 0x0001 /* read data, from slave to master */
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#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
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#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
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#define DW_IC_CON_MASTER 0x1
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#define DW_IC_CON_SPEED_STD 0x2
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#define DW_IC_CON_SPEED_FAST 0x4
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#define DW_IC_CON_10BITADDR_MASTER 0x10
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#define DW_IC_CON_RESTART_EN 0x20
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#define DW_IC_CON_SLAVE_DISABLE 0x40
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#define DW_IC_INTR_RX_UNDER 0x001
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#define DW_IC_INTR_RX_OVER 0x002
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#define DW_IC_INTR_RX_FULL 0x004
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#define DW_IC_INTR_TX_OVER 0x008
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#define DW_IC_INTR_TX_EMPTY 0x010
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#define DW_IC_INTR_RD_REQ 0x020
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#define DW_IC_INTR_TX_ABRT 0x040
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#define DW_IC_INTR_RX_DONE 0x080
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#define DW_IC_INTR_ACTIVITY 0x100
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#define DW_IC_INTR_STOP_DET 0x200
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#define DW_IC_INTR_START_DET 0x400
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#define DW_IC_INTR_GEN_CALL 0x800
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#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
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DW_IC_INTR_TX_EMPTY | \
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DW_IC_INTR_TX_ABRT | \
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DW_IC_INTR_STOP_DET)
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#define DW_IC_STATUS_ACTIVITY 0x1
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#define DW_IC_STATUS_MASTER_ACTIVITY 0x20
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#define DW_IC_ERR_TX_ABRT 0x1
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/*
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* status codes
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*/
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#define STATUS_IDLE 0x0
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#define STATUS_WRITE_IN_PROGRESS 0x1
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#define STATUS_READ_IN_PROGRESS 0x2
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#define TIMEOUT 20 /* ms */
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/*
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* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
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*
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* only expected abort codes are listed here
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* refer to the datasheet for the full list
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*/
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ABRT_MASTER_DIS 11
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#define ARB_LOST 12
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#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
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#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
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#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
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#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
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#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
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#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
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#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
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#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
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#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
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#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
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#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
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#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
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DW_IC_TX_ABRT_10ADDR1_NOACK | \
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DW_IC_TX_ABRT_10ADDR2_NOACK | \
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DW_IC_TX_ABRT_TXDATA_NOACK | \
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DW_IC_TX_ABRT_GCALL_NOACK)
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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"slave address not acknowledged (7bit mode)",
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[ABRT_10ADDR1_NOACK] =
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"first address byte not acknowledged (10bit mode)",
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[ABRT_10ADDR2_NOACK] =
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"second address byte not acknowledged (10bit mode)",
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[ABRT_TXDATA_NOACK] =
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"data not acknowledged",
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[ABRT_GCALL_NOACK] =
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"no acknowledgement for a general call",
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[ABRT_GCALL_READ] =
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"read after general call",
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[ABRT_SBYTE_ACKDET] =
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"start byte acknowledged",
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[ABRT_SBYTE_NORSTRT] =
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"trying to send start byte when restart is disabled",
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[ABRT_10B_RD_NORSTRT] =
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"trying to read when restart is disabled (10bit mode)",
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[ABRT_MASTER_DIS] =
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"trying to use disabled adapter",
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[ARB_LOST] =
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"lost arbitration",
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};
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/* i2c interrput definition */
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#define M_GEN_CALL (1<<11)
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#define M_START_DET (1<<10)
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#define M_STOP_DET (1<<9)
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#define M_ACTIVITY (1<<8)
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#define M_RX_DONE (1<<7)
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#define M_TX_ABRT (1<<6)
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#define M_RD_REQ (1<<5)
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#define M_TX_EMPTY (1<<4)
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#define M_TX_OVER (1<<3)
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#define M_RX_FULL (1<<2)
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#define M_RX_OVER (1<<1)
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#define M_RX_UNDER (1<<0)
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#define M_NONE (0)
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struct i2c_config
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{
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int speed_mode;
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UINT32 tx_fifo_depth;
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UINT32 rx_fifo_depth;
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};
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struct fh_i2c_obj
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{
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UINT32 id;
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UINT32 irq;
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UINT32 base;
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UINT32 input_clock;
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UINT32 abort_source;
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struct i2c_config config;
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};
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2017-12-25 15:52:17 +08:00
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rt_inline UINT32 I2C_SetTransmitThreshold(struct fh_i2c_obj *i2c_obj, int txtl)
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{
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return SET_REG(i2c_obj->base + OFFSET_I2C_TX_TL, txtl);
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}
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rt_inline UINT32 I2C_GetReceiveFifoLevel(struct fh_i2c_obj *i2c_obj)
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{
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return GET_REG(i2c_obj->base + OFFSET_I2C_RXFLR);
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}
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rt_inline UINT32 I2C_GetTransmitFifoLevel(struct fh_i2c_obj *i2c_obj)
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{
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return GET_REG(i2c_obj->base + OFFSET_I2C_TXFLR);
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}
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rt_inline void I2C_SetSlaveAddress(struct fh_i2c_obj *i2c_obj, rt_uint16_t addr)
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{
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UINT32 reg;
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reg = GET_REG(i2c_obj->base + OFFSET_I2C_TAR);
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reg &= ~(0x3ff);
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reg |= addr & 0x3ff;
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SET_REG(i2c_obj->base + OFFSET_I2C_TAR, reg);
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}
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rt_inline void I2C_Enable(struct fh_i2c_obj *i2c_obj, int enable)
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{
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SET_REG(i2c_obj->base + OFFSET_I2C_ENABLE, enable);
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}
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rt_inline UINT8 I2C_GetData(struct fh_i2c_obj *i2c_obj)
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{
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return GET_REG(i2c_obj->base + OFFSET_I2C_DATA_CMD) & 0xff;
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}
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rt_inline void I2C_SetDataCmd(struct fh_i2c_obj *i2c_obj, UINT32 reg)
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{
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SET_REG(i2c_obj->base + OFFSET_I2C_DATA_CMD, reg);
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}
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rt_inline void I2C_SetInterruptMask(struct fh_i2c_obj *i2c_obj, UINT32 mask)
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{
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SET_REG(i2c_obj->base + OFFSET_I2C_INTR_MASK, mask);
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}
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rt_inline UINT32 I2C_GetInterruptMask(struct fh_i2c_obj *i2c_obj)
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{
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return GET_REG(i2c_obj->base + OFFSET_I2C_INTR_MASK);
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}
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2016-04-18 13:52:39 +08:00
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void I2C_Init(struct fh_i2c_obj *i2c_obj);
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int I2C_HandleTxAbort(struct fh_i2c_obj *i2c_obj);
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UINT32 I2C_ClearAndGetInterrupts(struct fh_i2c_obj *i2c_obj);
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int I2C_WaitMasterIdle(struct fh_i2c_obj *i2c_obj);
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int I2C_WaitDeviceIdle(struct fh_i2c_obj *i2c_obj);
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#endif /* FH_I2C_H_ */
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