203 lines
9.1 KiB
C
203 lines
9.1 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexbus.h"
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base FLEXBUS peripheral base address
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*
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* @return The FLEXBUS instance
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*/
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static uint32_t FLEXBUS_GetInstance(FB_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to FLEXBUS bases for each instance. */
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static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to FLEXBUS clocks for each instance. */
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static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t FLEXBUS_GetInstance(FB_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_flexbusBases); instance++)
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{
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if (s_flexbusBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_flexbusBases));
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return instance;
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}
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void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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{
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assert(config != NULL);
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assert(config->chip < FB_CSAR_COUNT);
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assert(config->waitStates <= 0x3FU);
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uint32_t chip = 0;
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uint32_t reg_value = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate clock for FLEXBUS */
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CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset all the register to default state */
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for (chip = 0; chip < FB_CSAR_COUNT; chip++)
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{
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/* Reset CSMR register, all chips not valid (disabled) */
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base->CS[chip].CSMR = 0x0000U;
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/* Set default base address */
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base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
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/* Reset FB_CSCRx register */
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base->CS[chip].CSCR = 0x0000U;
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}
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/* Set FB_CSPMCR register */
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/* FlexBus signal group 1 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
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/* FlexBus signal group 2 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
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/* FlexBus signal group 3 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
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/* FlexBus signal group 4 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
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/* FlexBus signal group 5 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
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/* Write to CSPMCR register */
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base->CSPMCR = reg_value;
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/* Update chip value */
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chip = config->chip;
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/* Base address */
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reg_value = config->chipBaseAddress;
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/* Write to CSAR register */
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base->CS[chip].CSAR = reg_value;
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/* Chip-select validation */
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reg_value = 0x1U << FB_CSMR_V_SHIFT;
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/* Write protect */
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reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT;
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/* Base address mask */
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reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;
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/* Write to CSMR register */
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base->CS[chip].CSMR = reg_value;
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/* Burst write */
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reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT;
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/* Burst read */
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reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT;
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/* Byte-enable mode */
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reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
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/* Port size */
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reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;
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/* The internal transfer acknowledge for accesses */
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reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
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/* Byte-Lane shift */
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reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;
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/* The number of wait states */
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reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT;
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/* Write address hold or deselect */
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reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT;
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/* Read address hold or deselect */
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reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT;
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/* Address setup */
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reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;
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/* Extended transfer start/extended address latch */
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reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
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/* Secondary wait state */
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reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT;
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/* Write to CSCR register */
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base->CS[chip].CSCR = reg_value;
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/* FlexBus signal group 1 multiplex control */
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reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
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/* FlexBus signal group 2 multiplex control */
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reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT;
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/* FlexBus signal group 3 multiplex control */
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reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT;
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/* FlexBus signal group 4 multiplex control */
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reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT;
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/* FlexBus signal group 5 multiplex control */
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reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
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/* Write to CSPMCR register */
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base->CSPMCR = reg_value;
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}
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void FLEXBUS_Deinit(FB_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate clock for FLEXBUS */
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CLOCK_DisableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
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{
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config->chip = 0; /* Chip 0 FlexBus for validation */
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config->writeProtect = 0; /* Write accesses are allowed */
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config->burstWrite = 0; /* Burst-Write disable */
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config->burstRead = 0; /* Burst-Read disable */
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config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */
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config->autoAcknowledge = true; /* Auto-Acknowledge enable */
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config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */
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config->secondaryWaitStates = 0; /* Secondary wait state disable */
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config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
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config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
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config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
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config->addressSetup =
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kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
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config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */
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config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */
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config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */
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config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */
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config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */
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config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */
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}
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