224 lines
6.7 KiB
C
224 lines
6.7 KiB
C
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-12-04 Tanek first implementation
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*/
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#include <stdint.h>
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#include <rthw.h>
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#include <rtthread.h>
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static uint32_t _RDWORD(uint32_t address)
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{
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return *((uint32_t *)address);
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}
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static void _WDWORD(uint32_t address, uint32_t value)
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{
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*((uint32_t *)address) = value;
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}
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static void SDRAM_WaitIpCmdDone(void)
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{
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unsigned long reg;
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do
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{
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reg = _RDWORD(0x402F003C);
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}while((reg & 0x3) == 0);
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}
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static void _clock_init(void)
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{
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unsigned long reg;
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// Enable all clocks
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_WDWORD(0x400FC068,0xffffffff);
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_WDWORD(0x400FC06C,0xffffffff);
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_WDWORD(0x400FC070,0xffffffff);
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_WDWORD(0x400FC074,0xffffffff);
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_WDWORD(0x400FC078,0xffffffff);
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_WDWORD(0x400FC07C,0xffffffff);
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_WDWORD(0x400FC080,0xffffffff);
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_WDWORD(0x400D8030,0x00002001);
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_WDWORD(0x400D8100,0x001d0000);
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_WDWORD(0x400FC014,0x00010D40);
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// // Enable SYS PLL
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// _WDWORD(0x400D8030,0x00002001);
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// do
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// {
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// reg = _RDWORD(0x400D8030);
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// }while((reg & 0x80000000) == 0);
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// // Ungate SYS PLL PFD2
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// reg = _RDWORD(0x400D8100);
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// reg &= ~0x800000;
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// _WDWORD(0x400D8100,reg);
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// // SEMC clock source selection.
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// // SDRAM running at 133Mhz
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// // CBCDR:
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// // SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
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// // SEMC_CLK_SEL: 1 SEMC_ALT_CLK
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// // SEMC_PODF: 2 divide by 3
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// reg = _RDWORD(0x400FC014);
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// reg |= 0x20040;
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// _WDWORD(0x400FC014,reg);
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// // Disable MPU which will be enabled by ROM to prevent code execution
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// reg = _RDWORD(0xE000ED94);
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// reg &= ~0x1;
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// _WDWORD(0xE000ED94, reg);
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}
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static void _sdr_Init(void)
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{
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// Config IOMUX
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_WDWORD(0x401F8014, 0x00000000);
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_WDWORD(0x401F8018, 0x00000000);
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_WDWORD(0x401F801C, 0x00000000);
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_WDWORD(0x401F8020, 0x00000000);
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_WDWORD(0x401F8024, 0x00000000);
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_WDWORD(0x401F8028, 0x00000000);
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_WDWORD(0x401F802C, 0x00000000);
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_WDWORD(0x401F8030, 0x00000000);
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_WDWORD(0x401F8034, 0x00000000);
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_WDWORD(0x401F8038, 0x00000000);
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_WDWORD(0x401F803C, 0x00000000);
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_WDWORD(0x401F8040, 0x00000000);
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_WDWORD(0x401F8044, 0x00000000);
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_WDWORD(0x401F8048, 0x00000000);
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_WDWORD(0x401F804C, 0x00000000);
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_WDWORD(0x401F8050, 0x00000000);
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_WDWORD(0x401F8054, 0x00000000);
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_WDWORD(0x401F8058, 0x00000000);
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_WDWORD(0x401F805C, 0x00000000);
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_WDWORD(0x401F8060, 0x00000000);
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_WDWORD(0x401F8064, 0x00000000);
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_WDWORD(0x401F8068, 0x00000000);
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_WDWORD(0x401F806C, 0x00000000);
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_WDWORD(0x401F8070, 0x00000000);
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_WDWORD(0x401F8074, 0x00000000);
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_WDWORD(0x401F8078, 0x00000000);
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_WDWORD(0x401F807C, 0x00000000);
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_WDWORD(0x401F8080, 0x00000000);
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_WDWORD(0x401F8084, 0x00000010); // EMC_28, DQS PIN, enable SION
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_WDWORD(0x401F8088, 0x00000000);
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_WDWORD(0x401F808C, 0x00000000);
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_WDWORD(0x401F8090, 0x00000000);
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_WDWORD(0x401F8094, 0x00000000);
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_WDWORD(0x401F8098, 0x00000000);
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_WDWORD(0x401F809C, 0x00000000);
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_WDWORD(0x401F80A0, 0x00000000);
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_WDWORD(0x401F80A4, 0x00000000);
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_WDWORD(0x401F80A8, 0x00000000);
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_WDWORD(0x401F80AC, 0x00000000);
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_WDWORD(0x401F80B0, 0x00000000);
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_WDWORD(0x401F80B4, 0x00000000);
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_WDWORD(0x401F80B8, 0x00000000);
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// PAD ctrl
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// drive strength = 0x7 to increase drive strength
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// otherwise the data7 bit may fail.
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_WDWORD(0x401F8204, 0x000000F1);
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_WDWORD(0x401F8208, 0x000000F1);
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_WDWORD(0x401F820C, 0x000000F1);
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_WDWORD(0x401F8210, 0x000000F1);
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_WDWORD(0x401F8214, 0x000000F1);
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_WDWORD(0x401F8218, 0x000000F1);
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_WDWORD(0x401F821C, 0x000000F1);
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_WDWORD(0x401F8220, 0x000000F1);
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_WDWORD(0x401F8224, 0x000000F1);
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_WDWORD(0x401F8228, 0x000000F1);
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_WDWORD(0x401F822C, 0x000000F1);
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_WDWORD(0x401F8230, 0x000000F1);
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_WDWORD(0x401F8234, 0x000000F1);
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_WDWORD(0x401F8238, 0x000000F1);
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_WDWORD(0x401F823C, 0x000000F1);
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_WDWORD(0x401F8240, 0x000000F1);
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_WDWORD(0x401F8244, 0x000000F1);
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_WDWORD(0x401F8248, 0x000000F1);
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_WDWORD(0x401F824C, 0x000000F1);
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_WDWORD(0x401F8250, 0x000000F1);
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_WDWORD(0x401F8254, 0x000000F1);
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_WDWORD(0x401F8258, 0x000000F1);
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_WDWORD(0x401F825C, 0x000000F1);
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_WDWORD(0x401F8260, 0x000000F1);
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_WDWORD(0x401F8264, 0x000000F1);
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_WDWORD(0x401F8268, 0x000000F1);
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_WDWORD(0x401F826C, 0x000000F1);
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_WDWORD(0x401F8270, 0x000000F1);
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_WDWORD(0x401F8274, 0x000000F1);
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_WDWORD(0x401F8278, 0x000000F1);
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_WDWORD(0x401F827C, 0x000000F1);
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_WDWORD(0x401F8280, 0x000000F1);
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_WDWORD(0x401F8284, 0x000000F1);
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_WDWORD(0x401F8288, 0x000000F1);
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_WDWORD(0x401F828C, 0x000000F1);
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_WDWORD(0x401F8290, 0x000000F1);
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_WDWORD(0x401F8294, 0x000000F1);
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_WDWORD(0x401F8298, 0x000000F1);
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_WDWORD(0x401F829C, 0x000000F1);
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_WDWORD(0x401F82A0, 0x000000F1);
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_WDWORD(0x401F82A4, 0x000000F1);
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_WDWORD(0x401F82A8, 0x000000F1);
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// Config SDR Controller Registers/
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_WDWORD(0x402F0000,0x10000004); // MCR
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_WDWORD(0x402F0008,0x00030524); // BMCR0
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_WDWORD(0x402F000C,0x06030524); // BMCR1
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_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
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_WDWORD(0x402F0014,0x8200001B); // BR1, 32MB
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_WDWORD(0x402F0018,0x8400001B); // BR2, 32MB
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_WDWORD(0x402F001C,0x8600001B); // BR3, 32MB
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_WDWORD(0x402F0020,0x90000021); // BR4,
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_WDWORD(0x402F0024,0xA0000019); // BR5,
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_WDWORD(0x402F0028,0xA8000017); // BR6,
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_WDWORD(0x402F002C,0xA900001B); // BR7,
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_WDWORD(0x402F0030,0x00000021); // BR8,
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_WDWORD(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
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// _WDWORD(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
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_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
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_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
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_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
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_WDWORD(0x402F004C,0x50210A09); // SDRAMCR3
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_WDWORD(0x402F0080,0x00000021); // DBICR0
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_WDWORD(0x402F0084,0x00888888); // DBICR1
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_WDWORD(0x402F0094,0x00000002); // IPCR1
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_WDWORD(0x402F0098,0x00000000); // IPCR2
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_WDWORD(0x402F0090,0x80000000); // IPCR0
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_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
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SDRAM_WaitIpCmdDone();
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_WDWORD(0x402F0090,0x80000000); // IPCR0
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_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
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SDRAM_WaitIpCmdDone();
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_WDWORD(0x402F0090,0x80000000); // IPCR0
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_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
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SDRAM_WaitIpCmdDone();
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_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
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_WDWORD(0x402F0090,0x80000000); // IPCR0
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_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
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SDRAM_WaitIpCmdDone();
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_WDWORD(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
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}
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int imxrt_sdram_init(void)
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{
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_clock_init();
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_sdr_Init();
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return 0;
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}
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/*@}*/
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