2021-09-03 11:50:17 +08:00
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ARM Macro Assembler Page 1
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1 00000000 ;/*
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2023-03-31 16:49:48 +08:00
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2 00000000 ; * Copyright (c) 2006-2022, RT-Thread Development Team
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2021-09-03 11:50:17 +08:00
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3 00000000 ; *
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4 00000000 ; * SPDX-License-Identifier: Apache-2.0
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5 00000000 ; *
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6 00000000 ; * Change Logs:
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7 00000000 ; * Date Author Notes
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8 00000000 ; * 2009-01-17 Bernard first version
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9 00000000 ; * 2013-06-18 aozima add restore MSP feature.
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10 00000000 ; * 2013-07-09 aozima enhancement hard fault e
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xception handler.
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11 00000000 ; */
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12 00000000
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13 00000000 ;/**
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14 00000000 ; * @addtogroup CORTEX-M3
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15 00000000 ; */
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16 00000000 ;/*@{*/
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17 00000000
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18 00000000 E000ED08
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SCB_VTOR
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EQU 0xE000ED08 ; Vector Table Offs
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et Register
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19 00000000 E000ED04
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NVIC_INT_CTRL
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EQU 0xE000ED04 ; interrupt control
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state register
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20 00000000 E000ED20
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NVIC_SYSPRI2
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EQU 0xE000ED20 ; system priority r
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egister (2)
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21 00000000 FFFF0000
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NVIC_PENDSV_PRI
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EQU 0xFFFF0000 ; PendSV and SysTic
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k priority value (l
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owest)
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22 00000000 10000000
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NVIC_PENDSVSET
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EQU 0x10000000 ; value to trigger
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PendSV exception
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23 00000000
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24 00000000 AREA |.text|, CODE, READONLY, ALIGN=
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2
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25 00000000 THUMB
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26 00000000 REQUIRE8
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27 00000000 PRESERVE8
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28 00000000
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29 00000000 IMPORT rt_thread_switch_interrupt_flag
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30 00000000 IMPORT rt_interrupt_from_thread
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31 00000000 IMPORT rt_interrupt_to_thread
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32 00000000
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33 00000000 ;/*
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34 00000000 ; * rt_base_t rt_hw_interrupt_disable();
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35 00000000 ; */
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36 00000000 rt_hw_interrupt_disable
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PROC
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37 00000000 EXPORT rt_hw_interrupt_disable
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38 00000000 F3EF 8010 MRS r0, PRIMASK
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39 00000004 B672 CPSID I
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ARM Macro Assembler Page 2
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40 00000006 4770 BX LR
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41 00000008 ENDP
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42 00000008
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43 00000008 ;/*
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44 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level);
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45 00000008 ; */
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46 00000008 rt_hw_interrupt_enable
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PROC
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47 00000008 EXPORT rt_hw_interrupt_enable
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48 00000008 F380 8810 MSR PRIMASK, r0
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49 0000000C 4770 BX LR
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50 0000000E ENDP
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51 0000000E
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52 0000000E ;/*
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53 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32
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to);
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54 0000000E ; * r0 --> from
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55 0000000E ; * r1 --> to
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56 0000000E ; */
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57 0000000E rt_hw_context_switch_interrupt
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58 0000000E EXPORT rt_hw_context_switch_interrupt
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59 0000000E rt_hw_context_switch
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PROC
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60 0000000E EXPORT rt_hw_context_switch
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61 0000000E
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62 0000000E ; set rt_thread_switch_interrupt_flag to 1
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63 0000000E 4A34 LDR r2, =rt_thread_switch_interrupt
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_flag
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64 00000010 6813 LDR r3, [r2]
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65 00000012 2B01 CMP r3, #1
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66 00000014 D004 BEQ _reswitch
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67 00000016 F04F 0301 MOV r3, #1
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68 0000001A 6013 STR r3, [r2]
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69 0000001C
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70 0000001C 4A31 LDR r2, =rt_interrupt_from_thread ;
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set rt_interrupt_f
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rom_thread
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71 0000001E 6010 STR r0, [r2]
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72 00000020
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73 00000020 _reswitch
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74 00000020 4A31 LDR r2, =rt_interrupt_to_thread ; s
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et rt_interrupt_to_
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thread
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75 00000022 6011 STR r1, [r2]
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76 00000024
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77 00000024 4831 LDR r0, =NVIC_INT_CTRL ; trigger th
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2021-09-03 11:50:17 +08:00
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e PendSV exception
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(causes context swi
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tch)
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78 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET
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79 0000002A 6001 STR r1, [r0]
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80 0000002C 4770 BX LR
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81 0000002E ENDP
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82 0000002E
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83 0000002E ; r0 --> switch from thread stack
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84 0000002E ; r1 --> switch to thread stack
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85 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from
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] stack
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86 0000002E PendSV_Handler
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ARM Macro Assembler Page 3
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PROC
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87 0000002E EXPORT PendSV_Handler
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88 0000002E
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89 0000002E ; disable interrupt to protect context switch
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90 0000002E F3EF 8210 MRS r2, PRIMASK
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91 00000032 B672 CPSID I
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92 00000034
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93 00000034 ; get rt_thread_switch_interrupt_flag
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94 00000034 482A LDR r0, =rt_thread_switch_interrupt
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_flag
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95 00000036 6801 LDR r1, [r0]
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96 00000038 B191 CBZ r1, pendsv_exit ; pendsv alread
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y handled
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97 0000003A
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98 0000003A ; clear rt_thread_switch_interrupt_flag to 0
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99 0000003A F04F 0100 MOV r1, #0x00
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100 0000003E 6001 STR r1, [r0]
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101 00000040
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102 00000040 4828 LDR r0, =rt_interrupt_from_thread
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103 00000042 6801 LDR r1, [r0]
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104 00000044 B129 CBZ r1, switch_to_thread ; skip reg
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ister save at the f
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irst time
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105 00000046
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106 00000046 F3EF 8109 MRS r1, psp ; get from thread s
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tack pointer
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107 0000004A E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11
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register
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108 0000004E 6800 LDR r0, [r0]
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109 00000050 6001 STR r1, [r0] ; update from threa
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d stack pointer
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110 00000052
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111 00000052 switch_to_thread
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112 00000052 4925 LDR r1, =rt_interrupt_to_thread
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113 00000054 6809 LDR r1, [r1]
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114 00000056 6809 LDR r1, [r1] ; load thread stack
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pointer
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115 00000058
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116 00000058 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11
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register
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117 0000005C F381 8809 MSR psp, r1 ; update stack poin
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ter
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118 00000060
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119 00000060 pendsv_exit
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120 00000060 ; restore interrupt
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121 00000060 F382 8810 MSR PRIMASK, r2
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122 00000064
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123 00000064 F04E 0E04 ORR lr, lr, #0x04
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124 00000068 4770 BX lr
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125 0000006A ENDP
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126 0000006A
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127 0000006A ;/*
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128 0000006A ; * void rt_hw_context_switch_to(rt_uint32 to);
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129 0000006A ; * r0 --> to
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130 0000006A ; * this fucntion is used to perform the first thread sw
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itch
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131 0000006A ; */
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132 0000006A rt_hw_context_switch_to
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PROC
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ARM Macro Assembler Page 4
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133 0000006A EXPORT rt_hw_context_switch_to
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134 0000006A ; set to thread
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135 0000006A 491F LDR r1, =rt_interrupt_to_thread
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2021-09-03 11:50:17 +08:00
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136 0000006C 6008 STR r0, [r1]
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137 0000006E
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138 0000006E ; set from thread to 0
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139 0000006E 491D LDR r1, =rt_interrupt_from_thread
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2021-09-03 11:50:17 +08:00
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140 00000070 F04F 0000 MOV r0, #0x0
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141 00000074 6008 STR r0, [r1]
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142 00000076
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143 00000076 ; set interrupt flag to 1
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144 00000076 491A LDR r1, =rt_thread_switch_interrupt
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2021-09-03 11:50:17 +08:00
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_flag
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145 00000078 F04F 0001 MOV r0, #1
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146 0000007C 6008 STR r0, [r1]
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147 0000007E
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148 0000007E ; set the PendSV and SysTick exception priority
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2023-03-31 16:49:48 +08:00
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149 0000007E 481C LDR r0, =NVIC_SYSPRI2
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150 00000080 491C LDR r1, =NVIC_PENDSV_PRI
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2021-09-03 11:50:17 +08:00
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151 00000082 F8D0 2000 LDR.W r2, [r0,#0x00] ; read
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152 00000086 EA41 0102 ORR r1,r1,r2 ; modify
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153 0000008A 6001 STR r1, [r0] ; write-back
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154 0000008C
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155 0000008C ; trigger the PendSV exception (causes context switch)
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156 0000008C 4817 LDR r0, =NVIC_INT_CTRL
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2021-09-03 11:50:17 +08:00
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157 0000008E F04F 5180 LDR r1, =NVIC_PENDSVSET
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158 00000092 6001 STR r1, [r0]
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159 00000094
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160 00000094 ; restore MSP
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161 00000094 4818 LDR r0, =SCB_VTOR
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2021-09-03 11:50:17 +08:00
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162 00000096 6800 LDR r0, [r0]
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163 00000098 6800 LDR r0, [r0]
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164 0000009A F380 8808 MSR msp, r0
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165 0000009E
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166 0000009E ; enable interrupts at processor level
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167 0000009E B661 CPSIE F
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168 000000A0 B662 CPSIE I
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169 000000A2
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170 000000A2 ; ensure PendSV exception taken place before subsequent
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operation
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171 000000A2 F3BF 8F4F DSB
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172 000000A6 F3BF 8F6F ISB
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173 000000AA
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174 000000AA ; never reach here!
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175 000000AA ENDP
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176 000000AA
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177 000000AA ; compatible with old version
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178 000000AA rt_hw_interrupt_thread_switch
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PROC
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179 000000AA EXPORT rt_hw_interrupt_thread_switch
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180 000000AA 4770 BX lr
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181 000000AC ENDP
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182 000000AC
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183 000000AC IMPORT rt_hw_hard_fault_exception
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184 000000AC EXPORT HardFault_Handler
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185 000000AC HardFault_Handler
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PROC
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186 000000AC
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187 000000AC ; get current context
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2021-09-03 11:50:17 +08:00
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ARM Macro Assembler Page 5
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2023-03-31 16:49:48 +08:00
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188 000000AC F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2]
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)
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189 000000B0 BF0C ITE EQ
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190 000000B2 F3EF 8008 MRSEQ r0, msp ; [2]=0 ==> Z=1, ge
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t fault context fro
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m handler.
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191 000000B6 F3EF 8009 MRSNE r0, psp ; [2]=1 ==> Z=0, ge
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t fault context fro
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m thread.
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192 000000BA
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193 000000BA E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11
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register
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194 000000BE F840 ED04 STMFD r0!, {lr} ; push exec_return
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register
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195 000000C2
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196 000000C2 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2]
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)
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197 000000C6 BF0C ITE EQ
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198 000000C8 F380 8808 MSREQ msp, r0 ; [2]=0 ==> Z=1, up
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2021-09-03 11:50:17 +08:00
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date stack pointer
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to MSP.
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199 000000CC F380 8809 MSRNE psp, r0 ; [2]=1 ==> Z=0, up
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2021-09-03 11:50:17 +08:00
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date stack pointer
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to PSP.
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2023-03-31 16:49:48 +08:00
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200 000000D0
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201 000000D0 B500 PUSH {lr}
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202 000000D2 F7FF FFFE BL rt_hw_hard_fault_exception
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203 000000D6 F85D EB04 POP {lr}
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204 000000DA
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205 000000DA F04E 0E04 ORR lr, lr, #0x04
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206 000000DE 4770 BX lr
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207 000000E0 ENDP
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208 000000E0
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209 000000E0 ALIGN 4
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210 000000E0
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211 000000E0 END
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2021-09-03 11:50:17 +08:00
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00000000
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00000000
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00000000
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E000ED04
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E000ED20
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FFFF0000
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E000ED08
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Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
|
2023-03-31 16:49:48 +08:00
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ork --depend=.\output\context_rvds.d -o.\output\context_rvds.o -I.\RTE\_rt-thre
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ad_gd32f105 -ID:\software\KEIL_V5_ArmPacks\GigaDevice\GD32F10x_DFP\2.0.3\Device
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\Include -ID:\software\KEIL_V5\ARM\CMSIS\Include --predefine="__MICROLIB SETA 1
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" --predefine="__UVISION_VERSION SETA 530" --predefine="GD32F10X_CL SETA 1" --p
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redefine="USE_STDPERIPH_DRIVER SETA 1" --predefine="_RTE_ SETA 1" --list=.\list
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\context_rvds.lst ..\..\libcpu\arm\cortex-m3\context_rvds.S
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2021-09-03 11:50:17 +08:00
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
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Relocatable symbols
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.text 00000000
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Symbol: .text
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Definitions
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At line 24 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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None
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Comment: .text unused
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2023-03-31 16:49:48 +08:00
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HardFault_Handler 000000AC
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2021-09-03 11:50:17 +08:00
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Symbol: HardFault_Handler
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Definitions
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2023-03-31 16:49:48 +08:00
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At line 185 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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2021-09-03 11:50:17 +08:00
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Uses
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2023-03-31 16:49:48 +08:00
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At line 184 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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2021-09-03 11:50:17 +08:00
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Comment: HardFault_Handler used once
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PendSV_Handler 0000002E
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Symbol: PendSV_Handler
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Definitions
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At line 86 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 87 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: PendSV_Handler used once
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_reswitch 00000020
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Symbol: _reswitch
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Definitions
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At line 73 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 66 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: _reswitch used once
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pendsv_exit 00000060
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Symbol: pendsv_exit
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Definitions
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At line 119 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 96 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: pendsv_exit used once
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rt_hw_context_switch 0000000E
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Symbol: rt_hw_context_switch
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Definitions
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At line 59 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 60 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: rt_hw_context_switch used once
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rt_hw_context_switch_interrupt 0000000E
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Symbol: rt_hw_context_switch_interrupt
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Definitions
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At line 57 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 58 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: rt_hw_context_switch_interrupt used once
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rt_hw_context_switch_to 0000006A
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Symbol: rt_hw_context_switch_to
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ARM Macro Assembler Page 2 Alphabetic symbol ordering
|
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Relocatable symbols
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Definitions
|
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|
At line 132 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 133 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: rt_hw_context_switch_to used once
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rt_hw_interrupt_disable 00000000
|
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Symbol: rt_hw_interrupt_disable
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Definitions
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At line 36 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 37 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: rt_hw_interrupt_disable used once
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rt_hw_interrupt_enable 00000008
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Symbol: rt_hw_interrupt_enable
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Definitions
|
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At line 46 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 47 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: rt_hw_interrupt_enable used once
|
2023-03-31 16:49:48 +08:00
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rt_hw_interrupt_thread_switch 000000AA
|
2021-09-03 11:50:17 +08:00
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Symbol: rt_hw_interrupt_thread_switch
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Definitions
|
2023-03-31 16:49:48 +08:00
|
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|
At line 178 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
2021-09-03 11:50:17 +08:00
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Uses
|
2023-03-31 16:49:48 +08:00
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At line 179 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
2021-09-03 11:50:17 +08:00
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Comment: rt_hw_interrupt_thread_switch used once
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switch_to_thread 00000052
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Symbol: switch_to_thread
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Definitions
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At line 111 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 104 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: switch_to_thread used once
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12 symbols
|
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ARM Macro Assembler Page 1 Alphabetic symbol ordering
|
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|
Absolute symbols
|
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NVIC_INT_CTRL E000ED04
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Symbol: NVIC_INT_CTRL
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Definitions
|
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|
At line 19 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 77 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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At line 156 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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NVIC_PENDSVSET 10000000
|
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Symbol: NVIC_PENDSVSET
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Definitions
|
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|
At line 22 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 78 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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At line 157 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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NVIC_PENDSV_PRI FFFF0000
|
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Symbol: NVIC_PENDSV_PRI
|
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Definitions
|
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|
At line 21 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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At line 150 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Comment: NVIC_PENDSV_PRI used once
|
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|
|
NVIC_SYSPRI2 E000ED20
|
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|
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|
|
Symbol: NVIC_SYSPRI2
|
|
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|
|
Definitions
|
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|
At line 20 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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Uses
|
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|
|
At line 149 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
|
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|
|
Comment: NVIC_SYSPRI2 used once
|
|
|
|
|
SCB_VTOR E000ED08
|
|
|
|
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|
|
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|
|
Symbol: SCB_VTOR
|
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|
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Definitions
|
|
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|
|
At line 18 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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Uses
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|
At line 161 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
|
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|
|
Comment: SCB_VTOR used once
|
|
|
|
|
5 symbols
|
|
|
|
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|
|
|
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|
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|
|
|
|
|
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|
|
ARM Macro Assembler Page 1 Alphabetic symbol ordering
|
|
|
|
|
External symbols
|
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|
|
|
|
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|
|
rt_hw_hard_fault_exception 00000000
|
|
|
|
|
|
|
|
|
|
Symbol: rt_hw_hard_fault_exception
|
|
|
|
|
Definitions
|
2023-03-31 16:49:48 +08:00
|
|
|
At line 183 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
2021-09-03 11:50:17 +08:00
|
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Uses
|
2023-03-31 16:49:48 +08:00
|
|
|
At line 202 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
2021-09-03 11:50:17 +08:00
|
|
|
Comment: rt_hw_hard_fault_exception used once
|
|
|
|
|
rt_interrupt_from_thread 00000000
|
|
|
|
|
|
|
|
|
|
Symbol: rt_interrupt_from_thread
|
|
|
|
|
Definitions
|
|
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|
|
At line 30 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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Uses
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|
At line 70 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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At line 102 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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|
At line 139 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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|
|
|
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|
|
rt_interrupt_to_thread 00000000
|
|
|
|
|
|
|
|
|
|
Symbol: rt_interrupt_to_thread
|
|
|
|
|
Definitions
|
|
|
|
|
At line 31 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
|
|
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|
|
At line 74 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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|
At line 112 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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|
At line 135 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
|
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|
|
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|
|
rt_thread_switch_interrupt_flag 00000000
|
|
|
|
|
|
|
|
|
|
Symbol: rt_thread_switch_interrupt_flag
|
|
|
|
|
Definitions
|
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|
At line 29 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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Uses
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|
At line 63 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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|
At line 94 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
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|
At line 144 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S
|
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|
4 symbols
|
2023-03-31 16:49:48 +08:00
|
|
|
358 symbols in table
|
