296 lines
15 KiB
C
296 lines
15 KiB
C
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//###########################################################################
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//
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// FILE: hw_cmpss.h
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//
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// TITLE: Definitions for the C28x CMPSS registers.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __HW_CMPSS_H__
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#define __HW_CMPSS_H__
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//*****************************************************************************
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//
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// The following are defines for the CMPSS register offsets
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//
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//*****************************************************************************
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#define CMPSS_O_COMPCTL 0x0 // CMPSS Comparator Control
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// Register
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#define CMPSS_O_COMPHYSCTL 0x1 // CMPSS Comparator Hysteresis
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// Control Register
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#define CMPSS_O_COMPSTS 0x2 // CMPSS Comparator Status
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// Register
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#define CMPSS_O_COMPSTSCLR 0x3 // CMPSS Comparator Status Clear
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// Register
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#define CMPSS_O_COMPDACCTL 0x4 // CMPSS DAC Control Register
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#define CMPSS_O_DACHVALS 0x6 // CMPSS High DAC Value Shadow
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// Register
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#define CMPSS_O_DACHVALA 0x7 // CMPSS High DAC Value Active
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// Register
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#define CMPSS_O_RAMPMAXREFA 0x8 // CMPSS Ramp Max Reference Active
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// Register
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#define CMPSS_O_RAMPMAXREFS 0xA // CMPSS Ramp Max Reference Shadow
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// Register
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#define CMPSS_O_RAMPDECVALA 0xC // CMPSS Ramp Decrement Value
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// Active Register
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#define CMPSS_O_RAMPDECVALS 0xE // CMPSS Ramp Decrement Value
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// Shadow Register
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#define CMPSS_O_RAMPSTS 0x10 // CMPSS Ramp Status Register
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#define CMPSS_O_DACLVALS 0x12 // CMPSS Low DAC Value Shadow
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// Register
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#define CMPSS_O_DACLVALA 0x13 // CMPSS Low DAC Value Active
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// Register
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#define CMPSS_O_RAMPDLYA 0x14 // CMPSS Ramp Delay Active
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// Register
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#define CMPSS_O_RAMPDLYS 0x15 // CMPSS Ramp Delay Shadow
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// Register
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#define CMPSS_O_CTRIPLFILCTL 0x16 // CTRIPL Filter Control Register
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#define CMPSS_O_CTRIPLFILCLKCTL 0x17 // CTRIPL Filter Clock Control
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// Register
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#define CMPSS_O_CTRIPHFILCTL 0x18 // CTRIPH Filter Control Register
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#define CMPSS_O_CTRIPHFILCLKCTL 0x19 // CTRIPH Filter Clock Control
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// Register
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#define CMPSS_O_COMPLOCK 0x1A // CMPSS Lock Register
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the COMPCTL register
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//
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//*****************************************************************************
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#define CMPSS_COMPCTL_COMPHSOURCE 0x1 // High Comparator Source Select
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#define CMPSS_COMPCTL_COMPHINV 0x2 // High Comparator Invert Select
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#define CMPSS_COMPCTL_CTRIPHSEL_S 2
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#define CMPSS_COMPCTL_CTRIPHSEL_M 0xC // High Comparator Trip Select
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#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4
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#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30 // High Comparator Trip Output
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// Select
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#define CMPSS_COMPCTL_ASYNCHEN 0x40 // High Comparator Asynchronous
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// Path Enable
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#define CMPSS_COMPCTL_COMPLSOURCE 0x100 // Low Comparator Source Select
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#define CMPSS_COMPCTL_COMPLINV 0x200 // Low Comparator Invert Select
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#define CMPSS_COMPCTL_CTRIPLSEL_S 10
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#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00 // Low Comparator Trip Select
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#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12
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#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000 // Low Comparator Trip Output
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// Select
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#define CMPSS_COMPCTL_ASYNCLEN 0x4000 // Low Comparator Asynchronous
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// Path Enable
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#define CMPSS_COMPCTL_COMPDACE 0x8000 // Comparator/DAC Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the COMPHYSCTL register
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//
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//*****************************************************************************
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#define CMPSS_COMPHYSCTL_COMPHYS_S 0
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#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7 // Comparator Hysteresis Trim
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the COMPSTS register
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//
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//*****************************************************************************
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#define CMPSS_COMPSTS_COMPHSTS 0x1 // High Comparator Status
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#define CMPSS_COMPSTS_COMPHLATCH 0x2 // High Comparator Latched Status
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#define CMPSS_COMPSTS_COMPLSTS 0x100 // Low Comparator Status
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#define CMPSS_COMPSTS_COMPLLATCH 0x200 // Low Comparator Latched Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the COMPSTSCLR register
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//
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//*****************************************************************************
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#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2 // High Comparator Latched Status
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// Clear
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#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4 // High Comparator PWMSYNC Clear
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// Enable
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#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200 // Low Comparator Latched Status
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// Clear
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#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400 // Low Comparator PWMSYNC Clear
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// Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the COMPDACCTL register
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//
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//*****************************************************************************
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#define CMPSS_COMPDACCTL_DACSOURCE 0x1 // DAC Source Control
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#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1
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#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1E // Ramp Generator Source Control
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#define CMPSS_COMPDACCTL_SELREF 0x20 // DAC Reference Select
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#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40 // Ramp Load Select
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#define CMPSS_COMPDACCTL_SWLOADSEL 0x80 // Software Load Select
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#define CMPSS_COMPDACCTL_FREESOFT_S 14
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#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000 // Free/Soft Emulation Bits
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DACHVALS register
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//
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//*****************************************************************************
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#define CMPSS_DACHVALS_DACVAL_S 0
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#define CMPSS_DACHVALS_DACVAL_M 0xFFF // DAC Value Control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DACHVALA register
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//
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//*****************************************************************************
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#define CMPSS_DACHVALA_DACVAL_S 0
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#define CMPSS_DACHVALA_DACVAL_M 0xFFF // DAC Value Control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPMAXREFA register
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//
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//*****************************************************************************
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#define CMPSS_RAMPMAXREFA_RAMPMAXREF_S 0
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#define CMPSS_RAMPMAXREFA_RAMPMAXREF_M 0xFFFF // Ramp Maximum Reference Active
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPMAXREFS register
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//
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//*****************************************************************************
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#define CMPSS_RAMPMAXREFS_RAMPMAXREF_S 0
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#define CMPSS_RAMPMAXREFS_RAMPMAXREF_M 0xFFFF // Ramp Maximum Reference Shadow
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPDECVALA register
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//
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//*****************************************************************************
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#define CMPSS_RAMPDECVALA_RAMPDECVAL_S 0
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#define CMPSS_RAMPDECVALA_RAMPDECVAL_M 0xFFFF // Ramp Decrement Value Active
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPDECVALS register
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//
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//*****************************************************************************
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#define CMPSS_RAMPDECVALS_RAMPDECVAL_S 0
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#define CMPSS_RAMPDECVALS_RAMPDECVAL_M 0xFFFF // Ramp Decrement Value Shadow
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPSTS register
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//
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//*****************************************************************************
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#define CMPSS_RAMPSTS_RAMPVALUE_S 0
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#define CMPSS_RAMPSTS_RAMPVALUE_M 0xFFFF // Ramp Value
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DACLVALS register
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//
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//*****************************************************************************
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#define CMPSS_DACLVALS_DACVAL_S 0
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#define CMPSS_DACLVALS_DACVAL_M 0xFFF // DAC Value Control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the DACLVALA register
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//
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//*****************************************************************************
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#define CMPSS_DACLVALA_DACVAL_S 0
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#define CMPSS_DACLVALA_DACVAL_M 0xFFF // DAC Value Control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPDLYA register
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//
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//*****************************************************************************
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#define CMPSS_RAMPDLYA_DELAY_S 0
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#define CMPSS_RAMPDLYA_DELAY_M 0x1FFF // Ramp Delay Value
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the RAMPDLYS register
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//
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//*****************************************************************************
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#define CMPSS_RAMPDLYS_DELAY_S 0
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#define CMPSS_RAMPDLYS_DELAY_M 0x1FFF // Ramp Delay Value
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPLFILCTL register
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//
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//*****************************************************************************
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#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4
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#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0 // Sample Window
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#define CMPSS_CTRIPLFILCTL_THRESH_S 9
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#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00 // Majority Voting Threshold
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#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000 // Filter Initialization Bit
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPLFILCLKCTL register
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//
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//*****************************************************************************
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#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0
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#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FF // Sample Clock Prescale
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPHFILCTL register
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//
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//*****************************************************************************
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#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4
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#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0 // Sample Window
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#define CMPSS_CTRIPHFILCTL_THRESH_S 9
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#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00 // Majority Voting Threshold
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#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000 // Filter Initialization Bit
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CTRIPHFILCLKCTL register
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//
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//*****************************************************************************
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#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0
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#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FF // Sample Clock Prescale
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the COMPLOCK register
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//
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//*****************************************************************************
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#define CMPSS_COMPLOCK_COMPCTL 0x1 // COMPCTL Lock
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#define CMPSS_COMPLOCK_COMPHYSCTL 0x2 // COMPHYSCTL Lock
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#define CMPSS_COMPLOCK_DACCTL 0x4 // DACCTL Lock
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#define CMPSS_COMPLOCK_CTRIP 0x8 // CTRIP Lock
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#endif
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