153 lines
6.9 KiB
C
153 lines
6.9 KiB
C
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/*!
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\file gd32f10x_rtc.h
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\brief definitions for the RTC
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_RTC_H
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#define GD32F10X_RTC_H
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#include "gd32f10x.h"
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/* RTC definitions */
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#define RTC RTC_BASE
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/* registers definitions */
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#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */
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#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */
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#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */
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#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */
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#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */
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#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */
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#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */
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#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */
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#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */
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#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */
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/* bits definitions */
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/* RTC_INTEN */
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#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
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#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
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#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
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/* RTC_CTL */
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#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
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#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
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#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
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#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
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#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
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#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
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/* RTC_PSCH */
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#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
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/* RTC_PSCL */
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#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
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/* RTC_DIVH */
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#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
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/* RTC_DIVL */
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#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
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/* RTC_CNTH */
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#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
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/* RTC_CNTL */
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#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
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/* RTC_ALRMH */
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#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
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/* RTC_ALRML */
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#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
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/* constants definitions */
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/* RTC interrupt enable or disable definitions */
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#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
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#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
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#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
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/* RTC interrupt flag definitions */
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#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
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#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
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#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
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/* RTC flag definitions */
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#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
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#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
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#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
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#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
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#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
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/* function declarations */
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/* initialization functions */
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/* enter RTC configuration mode */
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void rtc_configuration_mode_enter(void);
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/* exit RTC configuration mode */
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void rtc_configuration_mode_exit(void);
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/* set RTC counter value */
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void rtc_counter_set(uint32_t cnt);
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/* set RTC prescaler value */
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void rtc_prescaler_set(uint32_t psc);
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/* operation functions */
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/* wait RTC last write operation finished flag set */
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void rtc_lwoff_wait(void);
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/* wait RTC registers synchronized flag set */
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void rtc_register_sync_wait(void);
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/* set RTC alarm value */
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void rtc_alarm_config(uint32_t alarm);
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/* get RTC counter value */
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uint32_t rtc_counter_get(void);
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/* get RTC divider value */
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uint32_t rtc_divider_get(void);
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/* flag & interrupt functions */
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/* get RTC flag status */
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FlagStatus rtc_flag_get(uint32_t flag);
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/* clear RTC flag status */
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void rtc_flag_clear(uint32_t flag);
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/* get RTC interrupt flag status */
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FlagStatus rtc_interrupt_flag_get(uint32_t flag);
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/* clear RTC interrupt flag status */
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void rtc_interrupt_flag_clear(uint32_t flag);
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/* enable RTC interrupt */
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void rtc_interrupt_enable(uint32_t interrupt);
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/* disable RTC interrupt */
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void rtc_interrupt_disable(uint32_t interrupt);
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#endif /* GD32F10X_RTC_H */
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