346 lines
12 KiB
C
346 lines
12 KiB
C
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/*
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* File : drv_sdio.h
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-29 zdzn first version
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*/
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#ifndef __DRV_SDIO_H__
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#define __DRV_SDIO_H__
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#include <rtthread.h>
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#define MMC0_BASE_ADDR 0x20300000
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struct raspi_mmc
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{
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volatile rt_uint32_t arg2_reg; /* (0x000) */
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volatile rt_uint32_t blksizecnt_reg; /* (0x004) */
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volatile rt_uint32_t arg1_reg; /* (0x008) */
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volatile rt_uint32_t cmdtm_reg; /* (0x00C) */
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volatile rt_uint32_t resp0_reg; /* (0x010) */
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volatile rt_uint32_t resp1_reg; /* (0x014) */
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volatile rt_uint32_t resp2_reg; /* (0x018) */
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volatile rt_uint32_t resp3_reg; /* (0x01C) */
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volatile rt_uint32_t data_reg; /* (0x020) */
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volatile rt_uint32_t status_reg; /* (0x024) */
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volatile rt_uint32_t control0_reg; /* (0x028) */
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volatile rt_uint32_t control1_reg; /* (0x02C) */
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volatile rt_uint32_t interrupt_reg; /* (0x030) */
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volatile rt_uint32_t irpt_mask_reg; /* (0x034) */
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volatile rt_uint32_t irpt_en_reg; /* (0x038) */
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volatile rt_uint32_t control2_reg; /* (0x03C) */
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volatile rt_uint32_t reserved1[4]; /* (0x040) */
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volatile rt_uint32_t force_irpt_reg; /* (0x050) */
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volatile rt_uint32_t reserved2[7]; /* (0x054) */
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volatile rt_uint32_t boot_timeout_reg; /* (0x070) */
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volatile rt_uint32_t deg_sel_reg; /* (0x074) */
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volatile rt_uint32_t reserved3[2]; /* (0x078) */
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volatile rt_uint32_t exrdfifo_cfg_reg; /* (0x080) */
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volatile rt_uint32_t exrdfifo_cn_reg; /* (0x084) */
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volatile rt_uint32_t tune_step_reg; /* (0x088) */
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volatile rt_uint32_t tune_step_std_reg; /* (0x08C) */
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volatile rt_uint32_t tune_step_ddr_reg; /* (0x090) */
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volatile rt_uint32_t reserved4[23]; /* (0x094) */
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volatile rt_uint32_t spi_int_reg; /* (0x0f0) */
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volatile rt_uint32_t reserved5[2]; /* (0x0f4) */
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volatile rt_uint32_t slotisr_ver_reg; /* (0x0fC) */
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};
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typedef struct raspi_mmc *raspi_mmc_t;
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#define MMC0 ((tina_mmc_t)MMC0_BASE_ADDR)
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#define BIT(x) (1<<(x))
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/* Struct for Intrrrupt Information */
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#define SDXC_CmdDone BIT(0)
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#define SDXC_DataDone BIT(1)
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#define SDXC_BlockGap BIT(2)
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#define SDXC_WriteRdy BIT(4)
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#define SDXC_ReadRdy BIT(5)
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#define SDXC_Card BIT(8)
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#define SDXC_Retune BIT(12)
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#define SDXC_BootAck BIT(13)
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#define SDXC_EndBoot BIT(14)
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#define SDXC_Err BIT(15)
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#define SDXC_CTOErr BIT(16)
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#define SDXC_CCRCErr BIT(17)
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#define SDXC_CENDErr BIT(18)
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#define SDXC_CBADErr BIT(19)
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#define SDXC_DTOErr BIT(20)
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#define SDXC_DCRCErr BIT(21)
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#define SDXC_DENDErr BIT(22)
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#define SDXC_ACMDErr BIT(24)
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/*
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SD CMD reg
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REG[0-5] : Cmd ID
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REG[6] : Has response
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REG[7] : Long response
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REG[8] : Check response CRC
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REG[9] : Has data
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REG[10] : Write
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REG[11] : Steam mode
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REG[12] : Auto stop
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REG[13] : Wait previous over
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REG[14] : About cmd
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REG[15] : Send initialization
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REG[21] : Update clock
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REG[31] : Load cmd
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*/
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#define SDXC_BLKCNT_EN BIT(1)
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#define SDXC_AUTO_CMD12_EN BIT(2)
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#define SDXC_AUTO_CMD23_EN BIT(3)
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#define SDXC_DAT_DIR BIT(4) //from card to host
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#define SDXC_MULTI_BLOCK BIT(5)
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#define SDXC_CMD_RSPNS_136 BIT(16)
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#define SDXC_CMD_RSPNS_48 BIT(17)
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#define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17)
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#define SDXC_CHECK_CRC_CMD BIT(19)
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#define SDXC_CMD_IXCHK_EN BIT(20)
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#define SDXC_CMD_ISDATA BIT(21)
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#define SDXC_CMD_SUSPEND BIT(22)
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#define SDXC_CMD_RESUME BIT(23)
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#define SDXC_CMD_ABORT BIT(23)|BIT(22)
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//#define SDXC_CHECK_CRC_CMD BIT(19)
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//
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//#define SDXC_RESPONSE_CMD BIT(6)
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//#define SDXC_LONG_RESPONSE_CMD BIT(7)
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//#define SDXC_CHECK_CRC_CMD BIT(8)
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//#define SDXC_HAS_DATA_CMD BIT(9)
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//#define SDXC_WRITE_CMD BIT(10)
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//#define SDXC_STEAM_CMD BIT(11)
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//#define SDXC_AUTO_STOP_CMD BIT(12)
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//#define SDXC_WAIT_OVER_CMD BIT(13)
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//#define SDXC_ABOUT_CMD BIT(14)
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//#define SDXC_SEND_INIT_CMD BIT(15)
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//#define SDXC_UPDATE_CLOCK_CMD BIT(21)
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//#define SDXC_LOAD_CMD BIT(31)
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/*
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SD status reg
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REG[0] : FIFO_RX_LEVEL
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REG[1] : FIFO_TX_LEVEL
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REG[2] : FIFO_EMPTY
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REG[3] : FIFO_FULL
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REG[4-7] : FSM_STA
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REG[8] : CARD_PRESENT
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REG[9] : CARD_BUSY
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REG[10] : FSM_BUSY
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REG[11-16]: RESP_IDX
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REG[17-21]: FIFO_LEVEL
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REG[31] : DMA_REQ
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*/
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#define SDXC_CMD_INHIBIT BIT(0)
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#define SDXC_DAT_INHIBIT BIT(1)
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#define SDXC_DAT_ACTIVE BIT(2)
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#define SDXC_WRITE_TRANSFER BIT(8)
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#define SDXC_READ_TRANSFER BIT(9)
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//
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//
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//#define SDXC_FIFO_RX_LEVEL BIT(0)
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//#define SDXC_FIFO_TX_LEVEL BIT(1)
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//#define SDXC_FIFO_EMPTY BIT(2)
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//#define SDXC_FIFO_FULL BIT(3)
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//#define SDXC_CARD_PRESENT BIT(8)
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//#define SDXC_CARD_BUSY BIT(9)
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//#define SDXC_FSM_BUSY BIT(10)
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//#define SDXC_DMA_REQ BIT(31)
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struct mmc_des_v4p1
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{
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rt_uint32_t : 1,
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dic : 1, /* disable interrupt on completion */
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last_des : 1, /* 1-this data buffer is the last buffer */
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first_des : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer */
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des_chain : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */
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end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */
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: 24,
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card_err_sum : 1, /* transfer error flag */
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own : 1; /* des owner:1-idma owns it, 0-host owns it */
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#define SDXC_DES_NUM_SHIFT 12 /* smhc2!! */
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#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
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rt_uint32_t data_buf1_sz : 16,
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data_buf2_sz : 16;
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rt_uint32_t buf_addr_ptr1;
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rt_uint32_t buf_addr_ptr2;
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};
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struct sdhci_cmd_t
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{
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rt_uint32_t cmdidx;
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rt_uint32_t cmdarg;
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//const char* name;
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// rt_uint32_t code;
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rt_uint32_t resptype;
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// rt_uint8_t rca;
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// rt_uint32_t delay;
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rt_uint32_t response[4];
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};
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struct sdhci_data_t
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{
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rt_uint8_t * buf;
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rt_uint32_t flag;
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rt_uint32_t blksz;
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rt_uint32_t blkcnt;
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};
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struct sdhci_t
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{
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char * name;
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rt_uint32_t voltages;
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rt_uint32_t width;
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rt_uint32_t clock;
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rt_err_t removeable;
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void * sdcard;
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rt_err_t (*detect)(struct sdhci_t * sdhci);
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rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width);
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rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock);
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rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat);
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void * priv;
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};
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struct sdhci_pdata_t
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{
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rt_uint32_t virt;
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};
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// EMMC command flags
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#define CMD_TYPE_NORMAL 0x00000000
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#define CMD_TYPE_SUSPEND 0x00400000
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#define CMD_TYPE_RESUME 0x00800000
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#define CMD_TYPE_ABORT 0x00c00000
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#define CMD_IS_DATA 0x00200000
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#define CMD_IXCHK_EN 0x00100000
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#define CMD_CRCCHK_EN 0x00080000
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#define CMD_RSPNS_NO 0x00000000
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#define CMD_RSPNS_136 0x00010000
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#define CMD_RSPNS_48 0x00020000
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#define CMD_RSPNS_48B 0x00030000
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#define TM_MULTI_BLOCK 0x00000020
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#define TM_DAT_DIR_HC 0x00000000
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#define TM_DAT_DIR_CH 0x00000010
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#define TM_AUTO_CMD23 0x00000008
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#define TM_AUTO_CMD12 0x00000004
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#define TM_BLKCNT_EN 0x00000002
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#define TM_MULTI_DATA (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN)
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// Response types.
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// Note that on the PI, the index and CRC are dropped, leaving 32 bits in RESP0.
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#define RESP_NO 0 // No response
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//#define RESP_R1 1 // 48 RESP0 contains card status
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#define RESP_R1b 11 // 48 RESP0 contains card status, data line indicates busy
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#define RESP_R2I 2 // 136 RESP0..3 contains 128 bit CID shifted down by 8 bits as no CRC
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#define RESP_R2S 12 // 136 RESP0..3 contains 128 bit CSD shifted down by 8 bits as no CRC
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//#define RESP_R3 3 // 48 RESP0 contains OCR register
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//#define RESP_R6 6 // 48 RESP0 contains RCA and status bits 23,22,19,12:0
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//#define RESP_R7 7 // 48 RESP0 contains voltage acceptance and check pattern
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#define RCA_NO 1
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#define RCA_YES 2
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// INTERRUPT register settings
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#define INT_AUTO_ERROR 0x01000000
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#define INT_DATA_END_ERR 0x00400000
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#define INT_DATA_CRC_ERR 0x00200000
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#define INT_DATA_TIMEOUT 0x00100000
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#define INT_INDEX_ERROR 0x00080000
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#define INT_END_ERROR 0x00040000
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#define INT_CRC_ERROR 0x00020000
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#define INT_CMD_TIMEOUT 0x00010000
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#define INT_ERR 0x00008000
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#define INT_ENDBOOT 0x00004000
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#define INT_BOOTACK 0x00002000
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#define INT_RETUNE 0x00001000
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#define INT_CARD 0x00000100
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#define INT_READ_RDY 0x00000020
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#define INT_WRITE_RDY 0x00000010
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#define INT_BLOCK_GAP 0x00000004
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#define INT_DATA_DONE 0x00000002
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#define INT_CMD_DONE 0x00000001
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#define INT_ERROR_MASK (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \
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INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \
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INT_ERR|INT_AUTO_ERROR)
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#define INT_ALL_MASK (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK)
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#define EMMC_ARG2 (0x00)
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#define EMMC_BLKSIZECNT (0x04)
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#define EMMC_ARG1 (0x08)
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#define EMMC_CMDTM (0x0c)
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#define EMMC_RESP0 (0x10)
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#define EMMC_RESP1 (0x14)
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#define EMMC_RESP2 (0x18)
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#define EMMC_RESP3 (0x1c)
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#define EMMC_DATA (0x20)
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#define EMMC_STATUS (0x24)
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#define EMMC_CONTROL0 (0x28)
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#define EMMC_CONTROL1 (0x2c)
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#define EMMC_INTERRUPT (0x30)
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#define EMMC_IRPT_MASK (0x34)
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#define EMMC_IRPT_EN (0x38)
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#define EMMC_CONTROL2 (0x3c)
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#define EMMC_BOOT_TIMEOUT (0x70)
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#define EMMC_EXRDFIFO_EN (0x84)
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#define EMMC_SPI_INT_SPT (0xf0)
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#define EMMC_SLOTISR_VER (0xfc)
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// CONTROL register settings
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#define C0_SPI_MODE_EN 0x00100000
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#define C0_HCTL_HS_EN 0x00000004
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#define C0_HCTL_DWITDH 0x00000002
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#define C1_SRST_DATA 0x04000000
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#define C1_SRST_CMD 0x02000000
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#define C1_SRST_HC 0x01000000
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#define C1_TOUNIT_DIS 0x000f0000
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#define C1_TOUNIT_MAX 0x000e0000
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#define C1_CLK_GENSEL 0x00000020
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#define C1_CLK_EN 0x00000004
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#define C1_CLK_STABLE 0x00000002
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#define C1_CLK_INTLEN 0x00000001
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#define FREQ_SETUP 400000 // 400 Khz
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#define FREQ_NORMAL 25000000 // 25 Mhz
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// SLOTISR_VER values
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#define HOST_SPEC_NUM 0x00ff0000
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#define HOST_SPEC_NUM_SHIFT 16
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||
|
|
#define HOST_SPEC_V3 2
|
||
|
|
#define HOST_SPEC_V2 1
|
||
|
|
#define HOST_SPEC_V1 0
|
||
|
|
|
||
|
|
// STATUS register settings
|
||
|
|
#define SR_DAT_LEVEL1 0x1e000000
|
||
|
|
#define SR_CMD_LEVEL 0x01000000
|
||
|
|
#define SR_DAT_LEVEL0 0x00f00000
|
||
|
|
#define SR_DAT3 0x00800000
|
||
|
|
#define SR_DAT2 0x00400000
|
||
|
|
#define SR_DAT1 0x00200000
|
||
|
|
#define SR_DAT0 0x00100000
|
||
|
|
#define SR_WRITE_PROT 0x00080000 // From SDHC spec v2, BCM says reserved
|
||
|
|
#define SR_READ_AVAILABLE 0x00000800 // ???? undocumented
|
||
|
|
#define SR_WRITE_AVAILABLE 0x00000400 // ???? undocumented
|
||
|
|
#define SR_READ_TRANSFER 0x00000200
|
||
|
|
#define SR_WRITE_TRANSFER 0x00000100
|
||
|
|
#define SR_DAT_ACTIVE 0x00000004
|
||
|
|
#define SR_DAT_INHIBIT 0x00000002
|
||
|
|
#define SR_CMD_INHIBIT 0x00000001
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|