2020-09-11 10:11:25 +08:00
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen header file for GPIO Driver
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*/
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#ifndef _DW_GPIO_H_
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#define _DW_GPIO_H_
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#include "drv_gpio.h"
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-08-06 17:21:19 +08:00
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typedef struct
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2020-09-11 10:11:25 +08:00
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{
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__IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */
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__IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */
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__IOM uint32_t PORT_CTL; /* Offset: 0x008 (W/R) PortA source register */
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} dw_gpio_reg_t;
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typedef struct
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{
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__IOM uint32_t INTEN; /* Offset: 0x000 (W/R) Interrupt enable register */
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__IOM uint32_t INTMASK; /* Offset: 0x004 (W/R) Interrupt mask register */
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__IOM uint32_t INTTYPE_LEVEL; /* Offset: 0x008 (W/R) Interrupt level register */
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__IOM uint32_t INT_POLARITY; /* Offset: 0x00c (W/R) Interrupt polarity register */
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__IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */
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__IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port */
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__IOM uint32_t revreg1; /* Offset: 0x018 (W/R) Reserve register */
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__OM uint32_t PORTA_EOI; /* Offset: 0x01c (W/R) Port clear interrupt register */
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__IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register */
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__IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register */
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__IOM uint32_t revreg2[2]; /* Offset: 0x028 (W/R) Reserve register */
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__IOM uint32_t LS_SYNC; /* Offset: 0x030 (W/R) Level-sensitive synchronization enable register */
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} dw_gpio_control_reg_t;
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#ifdef __cplusplus
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}
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#endif
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#endif
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