541 lines
11 KiB
C
541 lines
11 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-28 iysheng first version
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*/
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#include <board.h>
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#include <drivers/drv_comm.h>
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#include <drivers/drv_hwtimer.h>
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#ifdef BSP_USING_HWTIMER
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enum timer_index_E {
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#ifdef BSP_USING_HWTIMER0
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TIM0_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER2
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TIM2_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER3
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TIM3_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER4
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TIM4_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER5
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TIM5_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER6
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TIM6_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER7
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TIM7_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER8
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TIM8_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER9
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TIM9_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER10
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TIM10_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER11
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TIM11_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER12
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TIM12_INDEX,
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#endif
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#ifdef BSP_USING_HWTIMER13
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TIM13_INDEX,
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#endif
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};
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/*
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* static void __set_timerx_freq
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* Set freq with timerx
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*
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* @param timerx the pointer of TIMER_TypeDef
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* @param freq of the timer clock
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* @retval None
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*/
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static void __set_timerx_freq(TIMER_TypeDef *timerx, uint32_t freq)
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{
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RCC_ClocksPara RCC_Clocks = {0};
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uint16_t prescaler;
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uint32_t temp;
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RCC_GetClocksFreq(&RCC_Clocks);
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if (timerx == TIMER0 || timerx == TIMER7 || timerx == TIMER8 \
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|| timerx == TIMER9 || timerx == TIMER10)
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{
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temp = RCC->GCFGR & RCC_GCFGR_APB2PS;
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temp >>= 11;
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/* whether should frequency doubling */
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temp = (temp < 4) ? 0 : 1;
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prescaler = (RCC_Clocks.APB2_Frequency << temp) / freq - 1;
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}
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else
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{
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temp = RCC->GCFGR & RCC_GCFGR_APB1PS;
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temp >>= 8;
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/* whether should frequency doubling */
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temp = (temp < 4) ? 0 : 1;
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prescaler = (RCC_Clocks.APB1_Frequency << temp) / freq - 1;
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}
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TIMER_PrescalerConfig(timerx, prescaler, TIMER_PSC_RELOAD_NOW);
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}
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static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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TIMER_TypeDef * timer_base = timer->parent.user_data;
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TIMER_BaseInitPara TIMER_Init;
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RT_ASSERT(timer_base);
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if (state)
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{
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TIMER_InternalClockConfig(timer_base);
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TIMER_BaseStructInit(&TIMER_Init);
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TIMER_Init.TIMER_Period = timer->info->maxcnt;
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TIMER_BaseInit(timer_base, &TIMER_Init);
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__set_timerx_freq(timer_base, timer->info->maxfreq);
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}
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}
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static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \
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rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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TIMER_TypeDef * timer_base = timer->parent.user_data;
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if (mode == HWTIMER_MODE_ONESHOT)
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{
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TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_SINGLE);
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}
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else if (mode == HWTIMER_MODE_PERIOD)
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{
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TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_REPETITIVE);
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}
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TIMER_SetCounter(timer_base, 0);
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TIMER_SetAutoreload(timer_base, cnt - 1);
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TIMER_Enable(timer_base, ENABLE);
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return 0;
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}
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static void gd32_hwtimer_stop(struct rt_hwtimer_device *timer)
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{
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TIMER_TypeDef * timer_base = timer->parent.user_data;
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TIMER_Enable(timer_base, DISABLE);
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}
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static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer)
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{
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TIMER_TypeDef * timer_base = timer->parent.user_data;
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rt_uint32_t count;
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count = TIMER_GetCounter(timer_base);
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return count;
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}
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static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_t cmd, \
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void *args)
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{
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int ret = RT_EOK;
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rt_int32_t freq;
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rt_hwtimer_mode_t mode;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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freq = *(rt_uint32_t *)args;
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__set_timerx_freq(timer->parent.user_data, freq);
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break;
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default:
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rt_kprintf("invalid cmd:%x\n", cmd);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static const struct rt_hwtimer_ops g_gd32_hwtimer_ops = {
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gd32_hwtimer_init,
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gd32_hwtimer_start,
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gd32_hwtimer_stop,
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gd32_hwtimer_count_get,
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gd32_hwtimer_control,
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};
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static gd32_hwtimer_device g_gd32_hwtimer[] = {
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#ifdef BSP_USING_HWTIMER0
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{
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"timer0",
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{
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TIMER0,
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TIMER0_UP_IRQn,
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RCU_TIMER0,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER1
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{
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"timer1",
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{
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TIMER1,
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TIMER1_IRQn,
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RCU_TIMER1,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER2
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{
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"timer2",
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{
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TIMER2,
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TIMER2_IRQn,
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RCU_TIMER2,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER3
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{
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"timer3",
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{
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TIMER3,
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TIMER3_IRQn,
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RCU_TIMER3,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER4
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{
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"timer4",
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{
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TIMER4,
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TIMER4_IRQn,
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RCU_TIMER4,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER5
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{
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"timer5",
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{
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TIMER5,
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TIMER5_IRQn,
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RCU_TIMER5,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER6
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{
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"timer6",
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{
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TIMER6,
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TIMER6_IRQn,
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RCU_TIMER6,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER7
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{
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"timer7",
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{
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TIMER7,
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TIMER7_UP_IRQn,
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RCU_TIMER7,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER8
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{
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"timer8",
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{
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TIMER8,
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TIMER8_IRQn,
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RCU_TIMER8,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER9
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{
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"timer9",
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{
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TIMER9,
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TIMER9_IRQn,
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RCU_TIMER9,
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},
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{0},
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{
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1000000,
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1000,
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0xffff,
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0, /* count up mode */
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}
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},
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#endif
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#ifdef BSP_USING_HWTIMER10
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{
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"timer10",
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{
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TIMER10,
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TIMER10_IRQn,
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RCU_TIMER10,
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},
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{0},
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{
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1000000,
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1000,
|
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|
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0xffff,
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0, /* count up mode */
|
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}
|
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},
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#endif
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#ifdef BSP_USING_HWTIMER11
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{
|
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"timer11",
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|
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{
|
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|
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TIMER11,
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TIMER11_IRQn,
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RCU_TIMER11,
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},
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{0},
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|
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{
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1000000,
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1000,
|
||
|
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0xffff,
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0, /* count up mode */
|
||
|
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}
|
||
|
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},
|
||
|
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#endif
|
||
|
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#ifdef BSP_USING_HWTIMER12
|
||
|
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{
|
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|
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"timer12",
|
||
|
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{
|
||
|
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TIMER12,
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TIMER12_IRQn,
|
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RCU_TIMER12,
|
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|
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},
|
||
|
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{0},
|
||
|
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{
|
||
|
|
1000000,
|
||
|
|
1000,
|
||
|
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0xffff,
|
||
|
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0, /* count up mode */
|
||
|
|
}
|
||
|
|
},
|
||
|
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#endif
|
||
|
|
#ifdef BSP_USING_HWTIMER13
|
||
|
|
{
|
||
|
|
"timer13",
|
||
|
|
{
|
||
|
|
TIMER13,
|
||
|
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TIMER13_IRQn,
|
||
|
|
RCU_TIMER13,
|
||
|
|
},
|
||
|
|
{0},
|
||
|
|
{
|
||
|
|
1000000,
|
||
|
|
1000,
|
||
|
|
0xffff,
|
||
|
|
0, /* count up mode */
|
||
|
|
}
|
||
|
|
},
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER0
|
||
|
|
void TIMER0_UP_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER1
|
||
|
|
void TIMER1_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER2
|
||
|
|
void TIMER2_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER3
|
||
|
|
void TIMER3_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER4
|
||
|
|
void TIMER4_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER5
|
||
|
|
void TIMER5_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER6
|
||
|
|
void TIMER6_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef BSP_USING_HWTIMER7
|
||
|
|
void TIMER7_UP_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev);
|
||
|
|
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \
|
||
|
|
TIMER_INT_UPDATE);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static int rt_hwtimer_init(void)
|
||
|
|
{
|
||
|
|
int ret = 0, i = 0;
|
||
|
|
|
||
|
|
for (; i < ARRAY_SIZE(g_gd32_hwtimer); i++)
|
||
|
|
{
|
||
|
|
g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops;
|
||
|
|
g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info;
|
||
|
|
|
||
|
|
rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu);
|
||
|
|
NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0);
|
||
|
|
NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn);
|
||
|
|
TIMER_INTConfig(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UPDATE, ENABLE);
|
||
|
|
ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \
|
||
|
|
g_gd32_hwtimer[i].dev_name, g_gd32_hwtimer[i].hw_data.reg_base);
|
||
|
|
if (RT_EOK != ret)
|
||
|
|
{
|
||
|
|
rt_kprintf("failed register %s, err=%d\n", g_gd32_hwtimer[i].dev_name, \
|
||
|
|
ret);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hwtimer_init);
|
||
|
|
#endif
|