652 lines
22 KiB
C
652 lines
22 KiB
C
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/*!
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\file gd32f30x_dma.c
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\brief DMA driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2017-02-10, V1.0.1, firmware for GD32F30x
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*/
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#include "gd32f30x_dma.h"
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#define DMA_WRONG_HANDLE while(1){}
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static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
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/*!
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\brief deinitialize DMA a channel registers
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel is deinitialized
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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/* disable DMA a channel */
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
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/* reset DMA channel registers */
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DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
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DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
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DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
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DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
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DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
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}
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/*!
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\brief initialize DMA channel
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel is initialized
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[in] init_struct: the data needed to initialize DMA channel
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periph_addr: peripheral base address
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periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
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periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
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memory_addr: memory base address
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memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
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memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
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direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
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number: the number of remaining data to be transferred by the DMA
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priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
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\param[out] none
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\retval none
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*/
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void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct)
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{
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uint32_t ctl;
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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/* configure peripheral base address */
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DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr;
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/* configure memory base address */
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DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr;
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/* configure the number of remaining data to be transferred */
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DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK);
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/* configure peripheral transfer width,memory transfer width, */
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ctl = DMA_CHCTL(dma_periph, channelx);
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ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
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ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority);
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DMA_CHCTL(dma_periph, channelx) = ctl;
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/* configure peripheral increasing mode */
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if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){
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DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
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}else{
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
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}
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/* configure memory increasing mode */
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if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){
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DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
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}else{
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
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}
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/* configure the direction of data transfer */
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if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
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}else{
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DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
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}
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}
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/*!
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\brief enable DMA circulation mode
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
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}
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/*!
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\brief disable DMA circulation mode
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
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}
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/*!
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\brief enable memory to memory mode
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
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}
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/*!
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\brief disable memory to memory mode
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
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}
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/*!
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\brief enable DMA channel
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
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}
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/*!
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\brief disable DMA channel
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
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}
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/*!
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\brief set DMA peripheral base address
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to set peripheral base address
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[in] address: peripheral base address
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\param[out] none
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\retval none
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*/
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void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHPADDR(dma_periph, channelx) = address;
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}
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/*!
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\brief set DMA memory base address
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to set memory base address
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[in] address: memory base address
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\param[out] none
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\retval none
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*/
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void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHMADDR(dma_periph, channelx) = address;
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}
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/*!
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\brief set the number of remaining data to be transferred by the DMA
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to set number
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[in] number: the number of remaining data to be transferred by the DMA
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\param[out] none
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\retval none
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*/
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void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
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}
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/*!
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\brief get the number of remaining data to be transferred by the DMA
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel to set number
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[out] none
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\retval uint32_t: the number of remaining data to be transferred by the DMA
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*/
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uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
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{
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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return (uint32_t)DMA_CHCNT(dma_periph, channelx);
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}
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/*!
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\brief configure priority level of DMA channel
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[in] priority: priority Level of this channel
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\arg DMA_PRIORITY_LOW: low priority
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\arg DMA_PRIORITY_MEDIUM: medium priority
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\arg DMA_PRIORITY_HIGH: high priority
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\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
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\param[out] none
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\retval none
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*/
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void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
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{
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uint32_t ctl;
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if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
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DMA_WRONG_HANDLE
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}
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(dma_periph, channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_PRIO;
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ctl |= priority;
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DMA_CHCTL(dma_periph, channelx) = ctl;
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}
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/*!
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\brief configure transfer data size of memory
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\param[in] dma_periph: DMAx(x=0,1)
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\arg DMAx(x=0,1)
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\param[in] channelx: specify which DMA channel
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\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
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\param[in] mwidth: transfer data width of memory
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\arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
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\arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
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\arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
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\param[out] none
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\retval none
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*/
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void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
|
||
|
|
{
|
||
|
|
uint32_t ctl;
|
||
|
|
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
/* acquire DMA_CHxCTL register */
|
||
|
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||
|
|
/* assign regiser */
|
||
|
|
ctl &= ~DMA_CHXCTL_MWIDTH;
|
||
|
|
ctl |= mwidth;
|
||
|
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief configure transfer data size of peripheral
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] pwidth: transfer data width of peripheral
|
||
|
|
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
|
||
|
|
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
|
||
|
|
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
|
||
|
|
{
|
||
|
|
uint32_t ctl;
|
||
|
|
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
/* acquire DMA_CHxCTL register */
|
||
|
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||
|
|
/* assign regiser */
|
||
|
|
ctl &= ~DMA_CHXCTL_PWIDTH;
|
||
|
|
ctl |= pwidth;
|
||
|
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable next address increasement algorithm of memory
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable next address increasement algorithm of memory
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable next address increasement algorithm of peripheral
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable next address increasement algorithm of peripheral
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief configure the direction of data transfer on the channel
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] direction: specify the direction of data transfer
|
||
|
|
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
|
||
|
|
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
if(DMA_PERIPHERAL_TO_MEMORY == direction){
|
||
|
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
|
||
|
|
} else {
|
||
|
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check DMA flag is set or not
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel to get flag
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_FLAG_G: global interrupt flag of channel
|
||
|
|
\arg DMA_FLAG_FTF: full transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_HTF: half transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_ERR: error flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval FlagStatus: SET or RESET
|
||
|
|
*/
|
||
|
|
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
FlagStatus reval;
|
||
|
|
|
||
|
|
if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
|
||
|
|
reval = SET;
|
||
|
|
}else{
|
||
|
|
reval = RESET;
|
||
|
|
}
|
||
|
|
|
||
|
|
return reval;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief clear DMA a channel flag
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel to clear flag
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_FLAG_G: global interrupt flag of channel
|
||
|
|
\arg DMA_FLAG_FTF: full transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_HTF: half transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_ERR: error flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check DMA flag and interrupt enable bit is set or not
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel to get flag
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
|
||
|
|
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
|
||
|
|
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval FlagStatus: SET or RESET
|
||
|
|
*/
|
||
|
|
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
|
||
|
|
|
||
|
|
switch(flag){
|
||
|
|
case DMA_INT_FLAG_FTF:
|
||
|
|
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
|
||
|
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
|
||
|
|
break;
|
||
|
|
case DMA_INT_FLAG_HTF:
|
||
|
|
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
|
||
|
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
|
||
|
|
break;
|
||
|
|
case DMA_INT_FLAG_ERR:
|
||
|
|
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
|
||
|
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
if(interrupt_flag && interrupt_enable){
|
||
|
|
return SET;
|
||
|
|
}else{
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief clear DMA a channel flag
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel to clear flag
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_INT_FLAG_G: global interrupt flag of channel
|
||
|
|
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
|
||
|
|
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
|
||
|
|
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable DMA interrupt
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] source: specify which interrupt to enbale
|
||
|
|
one or more parameters can be selected which are shown as below
|
||
|
|
\arg DMA_INT_FTF: channel full transfer finish interrupt
|
||
|
|
\arg DMA_INT_HTF: channel half transfer finish interrupt
|
||
|
|
\arg DMA_INT_ERR: channel error interrupt
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CHCTL(dma_periph, channelx) |= source;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable DMA interrupt
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
|
||
|
|
\param[in] source: specify which interrupt to disbale
|
||
|
|
one or more parameters can be selected which are shown as below
|
||
|
|
\arg DMA_INT_FTF: channel full transfer finish interrupt
|
||
|
|
\arg DMA_INT_HTF: channel half transfer finish interrupt
|
||
|
|
\arg DMA_INT_ERR: channel error interrupt
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
||
|
|
{
|
||
|
|
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
|
||
|
|
DMA_WRONG_HANDLE
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CHCTL(dma_periph, channelx) &= ~source;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check whether peripheral and channels match
|
||
|
|
\param[in] dma_periph: DMAx(x=0,1)
|
||
|
|
\arg DMAx(x=0,1)
|
||
|
|
\param[in] channelx: specify which DMA channel
|
||
|
|
\arg DMA_CHx(x=0..6)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
ErrStatus val = SUCCESS;
|
||
|
|
|
||
|
|
if(DMA1 == dma_periph){
|
||
|
|
if(channelx > DMA_CH4){
|
||
|
|
val = ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return val;
|
||
|
|
}
|