618 lines
19 KiB
C
618 lines
19 KiB
C
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/*
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******************************************************************************
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* @file System_ACM32F0x0.c
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* @version V1.0.0
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* @date 2021
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* @brief System Source File, includes clock management, reset management
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* and IO configuration, ...
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******************************************************************************
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*/
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#include "ACM32Fxx_HAL.h"
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uint32_t gu32_SystemClock;
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uint32_t gu32_APBClock;
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RESET_REASON Reset_Reason_Save;
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/* System count in SysTick_Handler */
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volatile uint32_t gu32_SystemCount;
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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#if 0
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/*********************************************************************************
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* Function : HardFault_Handler
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* Description : Hard Fault handle, while(1) loop, wait for debug
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* Input : none
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* Output : none
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* Author : xwl
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**********************************************************************************/
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void HardFault_Handler(void)
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{
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while(1);
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}
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/*********************************************************************************
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* Function : SysTick_Handler
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* Description : System tick handler
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* Input : none
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* Output : none
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* Author : Chris_Kyle
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**********************************************************************************/
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void SysTick_Handler(void)
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{
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gu32_SystemCount++;
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}
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/*********************************************************************************
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* Function : System_SysTick_Init
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* Description : System Tick Init. Period is 1 ms
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* Input : none
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* Output : none
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* Author : Chris_Kyle
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**********************************************************************************/
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void System_SysTick_Init(void)
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{
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gu32_SystemCount = 0;
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SysTick_Config(gu32_SystemClock / 1000); //1ms/tick
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}
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#endif
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/*********************************************************************************
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* Function : System_SysTick_Off
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* Description : Turn off System Tick
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* Input : none
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* Output : none
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* Author : xwl
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**********************************************************************************/
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void System_SysTick_Off(void)
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{
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SysTick->CTRL = 0;
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}
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/*********************************************************************************
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* Function : System_Init
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* Description : Initialize the system clock
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* Input : none
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* Outpu : none
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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void System_Init(void)
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{
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SCU->RCR |= SCU_RCR_REMAP_EN;
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System_Set_Buzzer_Divider(80, FUNC_DISABLE); // disable clock out
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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/* Vector Table Relocation in Internal SRAM */
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SCU->VECTOROFFSET = SRAM_BASE | VECT_TAB_OFFSET | SCU_VECTOROFFSET_VOFFSETEN;
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#else
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/* Vector Table Relocation in Internal FLASH */
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SCU->VECTOROFFSET = EFLASH_BASE | VECT_TAB_OFFSET | SCU_VECTOROFFSET_VOFFSETEN;
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#endif
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/* Initialize the system clock */
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if (false == System_Clock_Init(DEFAULT_SYSTEM_CLOCK))
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{
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while(1);
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}
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#ifdef HAL_SYSTICK_ENABLED // To activate macro in ACM32Fxx_HAL.h
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System_SysTick_Init();
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#endif
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}
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/*********************************************************************************
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* Function : System_Clock_Init
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* Description : Clock init
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* Input : fu32_Clock: System core clock
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* Outpu : 0: success, other value: fail reason
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* Author : xwl Date : 2021
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**********************************************************************************/
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bool System_Clock_Init(uint32_t fu32_Clock)
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{
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uint32_t lu32_DIV, lu32_system_clk_source, lu32_result, lu32_timeout;
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lu32_system_clk_source = CLK_SRC_RC64M;
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SET_EFC_RD_WAIT(RD_WAIT_SET_DEFAULT)
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switch (fu32_Clock)
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{
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/* 64MHz */
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case 64000000: lu32_DIV = 1; break;
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/* 32MHz */
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case 32000000: lu32_DIV = 2; break;
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/* 16MHz */
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case 16000000: lu32_DIV = 4; break;
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/* 8MHz */
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case 8000000: lu32_DIV = 8; break;
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default: return false;
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}
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lu32_result = 0;
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if (lu32_system_clk_source == CLK_SRC_XTH_PLL)
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{
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lu32_timeout = 0;
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SCU->XTHCR = SCU_XTHCR_XTH_EN | SCU_XTHCR_READYTIME_32768;
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while (0 == (SCU->XTHCR & SCU_XTHCR_XTHRDY))
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{
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if (lu32_timeout == SYSTEM_TIMEOUT)
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{
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lu32_result = 1;
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break;
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}
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lu32_timeout++;
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}
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if (0 == lu32_result)
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{
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SCU->PLLCR |= SCU_PLLCR_PLL_EN;
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SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP);
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while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) )) {}
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#ifdef XTH_8M_CRYSTAL
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SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (1U << 12) | (0U << 16);
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#endif
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#ifdef XTH_12M_CRYSTAL
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SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (2U << 12) | (0U << 16);
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#endif
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SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1);
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SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN;
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while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) );
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/* Division Config */
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SCU->CCR2 = (SCU->CCR2 & (~0xFF)) | APB_CLK_DIV_0 | (lu32_DIV - 1);
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while((SCU->CCR2 & (1UL << 31)) == 0x00);
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/* Clock Select PLL */
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SCU->CCR1 = SYS_CLK_SRC_PLLCLK;
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}
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else
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{
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SCU->XTHCR &= (~SCU_XTHCR_XTH_EN);
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}
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}
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if ( (lu32_system_clk_source == CLK_SRC_RC64M) || (0 != lu32_result) )
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{
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/* Division Config */
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SCU->CCR2 = (SCU->CCR2 & (~0xFF)) | APB_CLK_DIV_0 | (lu32_DIV - 1);
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while((SCU->CCR2 & (1UL << 31)) == 0x00);
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/* Clock Select RCH */
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SCU->CCR1 = SYS_CLK_SRC_RCH;
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}
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gu32_SystemClock = fu32_Clock;
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gu32_APBClock = fu32_Clock;
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/* Eflash Config */
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//HAL_EFlash_Init(gu32_SystemClock);
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return true;
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}
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/*********************************************************************************
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* Function : System_Get_SystemClock
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* Description : get AHB clock frequency
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* Input : none
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* Outpu : frequency, measured as Hz
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* Author : Chris_Kyle Date : 2020
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**********************************************************************************/
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uint32_t System_Get_SystemClock(void)
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{
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return gu32_SystemClock;
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}
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/*********************************************************************************
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* Function : System_Get_APBClock
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* Description : get APB clock frequency
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* Input : none
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* Outpu : frequency, measured as Hz
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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uint32_t System_Get_APBClock(void)
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{
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return gu32_APBClock;
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}
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/*********************************************************************************
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* Function : System_Module_Reset
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* Description : reset module
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* Input : module id
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* Outpu : none
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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void System_Module_Reset(enum_RST_ID_t fe_ID_Index)
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{
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SCU->IPRST &= (~(1 << fe_ID_Index));
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System_Delay(2);
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SCU->IPRST |= (1 << fe_ID_Index);
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}
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/*********************************************************************************
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* Function : System_Module_Enable
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* Description : enable module clock
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* Input : module id
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* Outpu : none
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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void System_Module_Enable(enum_Enable_ID_t fe_ID_Index)
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{
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if (fe_ID_Index > 6)
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{
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SCU->IPCKENR1 |= (1U << (fe_ID_Index - 7) );
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}
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else
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{
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SCU->IPCKENR2 |= (1U << fe_ID_Index);
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}
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System_Delay(2);
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}
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/*********************************************************************************
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* Function : System_Module_Disable
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* Description : disable module clock
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* Input : module id
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* Outpu : none
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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void System_Module_Disable(enum_Enable_ID_t fe_ID_Index)
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{
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if (fe_ID_Index > 6)
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{
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SCU->IPCKENR1 &= ~(1U << (fe_ID_Index - 7));
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}
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else
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{
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SCU->IPCKENR2 &= ~(1U << fe_ID_Index);
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}
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}
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/*********************************************************************************
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* Function : System_Delay
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* Description : NOP delay
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* Input : count
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* Output : none
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* Author : Chris_Kyle
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**********************************************************************************/
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void System_Delay(volatile uint32_t fu32_Delay)
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{
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while (fu32_Delay--);
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}
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/*********************************************************************************
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* Function : System_Delay_MS
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* Description : ms delay. Use this Function must call System_SysTick_Init()
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* Input : delay period, measured as ms
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* Output : none
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* Author : Chris_Kyle
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**********************************************************************************/
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void System_Delay_MS(volatile uint32_t fu32_Delay)
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{
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uint32_t lu32_SystemCountBackup;
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lu32_SystemCountBackup = gu32_SystemCount;
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while ( (gu32_SystemCount - lu32_SystemCountBackup) < fu32_Delay);
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}
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/*********************************************************************************
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* Function : System_Enable_RC32K
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* Description : Enable RC32K, make sure RTC Domain Access is allowed
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* Input : none
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* Outpu : none
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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void System_Enable_RC32K(void)
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{
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PMU->ANACR |= RPMU_ANACR_RC32K_EN;
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while(!(PMU->ANACR & RPMU_ANACR_RC32K_RDY));
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}
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/*********************************************************************************
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* Function : System_Disable_RC32K
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* Description : Disable RC32K
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* Input : none
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* Outpu : none
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* Author : CWT Date : 2021
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**********************************************************************************/
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void System_Disable_RC32K(void)
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{
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PMU->ANACR &= (~RPMU_ANACR_RC32K_EN);
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}
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/*********************************************************************************
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* Function : System_Enable_XTAL
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* Description : Enable XTAL, make sure RTC Domain Access is allowed
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* Input : none
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* Outpu : none
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* Author : Chris_Kyle Date : 2021
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**********************************************************************************/
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void System_Enable_XTAL(void)
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{
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PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0);
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PMU->ANACR |= RPMU_ANACR_XTLEN;
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while(!(PMU->ANACR & RPMU_ANACR_XTLRDY));
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PMU->CR1 |= RTC_CLOCK_XTL;
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}
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/*********************************************************************************
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* Function : System_Disable_XTAL
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* Description : Disable XTAL
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* Input : none
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* Output : none
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* Author : CWT
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**********************************************************************************/
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void System_Disable_XTAL(void)
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{
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PMU->ANACR &= (~(RPMU_ANACR_XTLEN));
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}
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/*********************************************************************************
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* Function : System_Enable_Disable_RTC_Domain_Access
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* Description : Enable or Disable RTC Domain Access.
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* Input : enable or disable
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* Output : none
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* Author : CWT
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**********************************************************************************/
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void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable)
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{
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if (FUNC_DISABLE == enable_disable)
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{
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SCU->STOPCFG &= (~SCU_STOPCFG_RTC_WE);
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}
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else
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{
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SCU->STOPCFG |= SCU_STOPCFG_RTC_WE;
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System_Delay(1);
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RTC->WP = 0xCA53CA53U;
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}
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}
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/*********************************************************************************
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* Function : System_Enable_Disable_Reset
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* Description : Enable or Disable System Reset source.
|
||
|
|
* Input : none
|
||
|
|
* Output : none
|
||
|
|
* Author : CWT
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable)
|
||
|
|
{
|
||
|
|
switch(source)
|
||
|
|
{
|
||
|
|
/* reset source: from bit0 to bit3 */
|
||
|
|
case RESET_ENABLE_SOURCE_LVD:
|
||
|
|
case RESET_ENABLE_SOURCE_WDT:
|
||
|
|
case RESET_ENABLE_SOURCE_IWDT:
|
||
|
|
case RESET_ENABLE_SOURCE_LOCKUP:
|
||
|
|
|
||
|
|
if (FUNC_DISABLE == enable_disable)
|
||
|
|
{
|
||
|
|
SCU->RCR &= (~(1U << source));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
SCU->RCR |= (1U << source);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default: break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Reset_MCU
|
||
|
|
* Description : reset mcu
|
||
|
|
* Input : reset source
|
||
|
|
* Output : none
|
||
|
|
* Author : xwl
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Reset_MCU(RESET_SOURCE source)
|
||
|
|
{
|
||
|
|
switch(source)
|
||
|
|
{
|
||
|
|
case RESET_SOURCE_EFC:
|
||
|
|
{
|
||
|
|
SCU->RCR &= (~BIT29);
|
||
|
|
while(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
case RESET_SOURCE_NVIC_RESET:
|
||
|
|
{
|
||
|
|
NVIC_SystemReset();
|
||
|
|
while(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
case RESET_SOFT_RESET:
|
||
|
|
{
|
||
|
|
SCU->RCR &= (~BIT30);
|
||
|
|
while(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
default: break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Enter_Standby_Mode
|
||
|
|
* Description : try to enter standby mode
|
||
|
|
* Input : none
|
||
|
|
* Output : none
|
||
|
|
* Author : xwl Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Enter_Standby_Mode(void)
|
||
|
|
{
|
||
|
|
__set_PRIMASK(1); // disable interrupt
|
||
|
|
SysTick->CTRL = 0; // disable systick
|
||
|
|
SCU->STOPCFG |= BIT11; // set PDDS=1
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
__WFI();
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
System_Delay(100);
|
||
|
|
|
||
|
|
printfS("Enter Standby Mode Failed! \n"); // should not go here
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Clear_Stop_Wakeup
|
||
|
|
* Description : clear all stop setting and status
|
||
|
|
* Input : none
|
||
|
|
* Output : none
|
||
|
|
* Author : CWT Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Clear_Stop_Wakeup(void)
|
||
|
|
{
|
||
|
|
EXTI->IENR = 0;
|
||
|
|
EXTI->RTENR = 0;
|
||
|
|
EXTI->FTENR = 0;
|
||
|
|
EXTI->SWIER = 0;
|
||
|
|
EXTI->PDR = 0x7FFFFFU;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Enter_Stop_Mode
|
||
|
|
* Description : try to enter stop mode
|
||
|
|
* Input : STOPEntry: STOPENTRY_WFI or STOPENTRY_WFE
|
||
|
|
* Output : none
|
||
|
|
* Author : CWT Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Enter_Stop_Mode(uint8_t STOPEntry)
|
||
|
|
{
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
SCU->STOPCFG &= (~BIT11); // PDDS=0
|
||
|
|
|
||
|
|
System_SysTick_Off();
|
||
|
|
/* Select Stop mode entry */
|
||
|
|
if(STOPEntry == STOPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
__WFE(); /* Wait For Event */
|
||
|
|
}
|
||
|
|
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
#ifdef HAL_SYSTICK_ENABLED // To activate macro in ACM32Fxx_HAL.h
|
||
|
|
System_SysTick_Init();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Enter_Sleep_Mode
|
||
|
|
* Description : try to enter sleep mode
|
||
|
|
* Input : SleepEntry: SLEEPENTRY_WFI or SLEEPENTRY_WFE
|
||
|
|
* Output : none
|
||
|
|
* Author : CWT Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Enter_Sleep_Mode(uint8_t SleepEntry)
|
||
|
|
{
|
||
|
|
/* clear SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* Select Stop mode entry */
|
||
|
|
if(SleepEntry == SLEEPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
__WFE(); /*Wait For Event */
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Return_Last_Reset_Reason
|
||
|
|
* Description : Get System Last Reset Reason
|
||
|
|
* Input : none
|
||
|
|
* Output : RESET_REASON
|
||
|
|
* Author : CWT Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
RESET_REASON System_Return_Last_Reset_Reason(void)
|
||
|
|
{
|
||
|
|
RESET_REASON i = RESET_REASON_POR;
|
||
|
|
Reset_Reason_Save = RESET_REASON_POR;
|
||
|
|
|
||
|
|
for(i = RESET_REASON_POR; i >= RESET_REASON_POR12; i--)
|
||
|
|
{
|
||
|
|
if ((SCU->RSR) & (1U << i))
|
||
|
|
{
|
||
|
|
SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags
|
||
|
|
Reset_Reason_Save = i;
|
||
|
|
return i;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for(i = RESET_REASON_LOW_VOLTAGE; i <= RESET_REASON_SOFT; i++)
|
||
|
|
{
|
||
|
|
if ((SCU->RSR) & (1U << i))
|
||
|
|
{
|
||
|
|
SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags
|
||
|
|
Reset_Reason_Save = i;
|
||
|
|
return i;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return RESET_REASON_INVALID; // this should not happen
|
||
|
|
}
|
||
|
|
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Return_Saved_Reset_Reason
|
||
|
|
* Description : Get saved Reset Reason
|
||
|
|
* Input : none
|
||
|
|
* Output : RESET_REASON
|
||
|
|
* Author : CWT Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
RESET_REASON System_Return_Saved_Reset_Reason(void)
|
||
|
|
{
|
||
|
|
return Reset_Reason_Save;
|
||
|
|
}
|
||
|
|
/*********************************************************************************
|
||
|
|
* Function : System_Set_Buzzer_Divider
|
||
|
|
* Description : set buzzer divide factor
|
||
|
|
* Input :
|
||
|
|
div: div factor, if div = 80 then output buzzer freq=HCLK/80
|
||
|
|
enable: FUNC_DISABLE and FUNC_ENABLE
|
||
|
|
* Output : none
|
||
|
|
* Author : xwl Date : 2021
|
||
|
|
**********************************************************************************/
|
||
|
|
void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable)
|
||
|
|
{
|
||
|
|
if (FUNC_ENABLE == enable)
|
||
|
|
{
|
||
|
|
SCU->CLKOCR = (SCU->CLKOCR & (~(0x1FFFFU << 5) ) ) | (div << 5);
|
||
|
|
SCU->CLKOCR |= BIT23;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
SCU->CLKOCR &= (~BIT23);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|