362 lines
8.7 KiB
C
362 lines
8.7 KiB
C
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/**
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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******************************************************************************
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* @file drv_gpio.c
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* @author Jay Xu
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* @version V0.1
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* @date 2019/5/15
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* @brief GPIO Driver
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*
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******************************************************************************
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*/
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/** @addtogroup RKBSP_Driver_Reference
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* @{
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*/
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/** @addtogroup GPIO
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* @{
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*/
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/** @defgroup GPIO_How_To_Use How To Use
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* @{
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The GPIO driver use to configure or control GPIO pins on SoCs, it can be used in
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the following three scenarios:
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- (A) The GPIO PIN APIs provide by pin component:
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- 1) rt_pin_read - get pin level, pin number caculated by BANK_PIN(banknum, pinnum);
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- 2) rt_pin_write- set pin level, pin number caculated by BANK_PIN(banknum, pinnum);
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- 3) rt_pin_mode - set pin input/output, pin number caculated by BANK_PIN(banknum, pinnum);
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- (B) The GPIO IRQ APIs provide by pin component:
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- 1) pin_attach_irq;
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- 2) pin_detach_irq;
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- 3) pin_irq_enable;
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- (C) The GPIO PIN NUMBER calculated by BANK_PIN(b,p), such as
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BANK_PIN(0, 5) means GPIO0_A5
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BANK_PIN(1, 8) means GPIO1_B0
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See more information, click [here](http://www.rt-thread.org/document/site/programming-manual/device/pin/pin/)
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@} */
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtthread.h>
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#ifdef RT_USING_PIN
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#include "hal_base.h"
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#include "drv_gpio.h"
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/********************* Private MACRO Definition ******************************/
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#define PIN_NUM(p) ((p & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT)
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#define PIN_BANK(p) ((p & GPIO_BANK_MASK) >> GPIO_BANK_SHIFT)
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#define BANK_PIN_DEFAULT (-1)
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/********************* Private Structure Definition **************************/
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static struct GPIO_REG *GPIO_GROUP[] =
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{
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#ifdef GPIO0
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GPIO0,
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#endif
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#ifdef GPIO1
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GPIO1,
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#endif
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#ifdef GPIO2
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GPIO2,
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#endif
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#ifdef GPIO3
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GPIO3,
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#endif
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#ifdef GPIO4
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GPIO4,
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#endif
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};
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#define GPIO_BANK_NUM HAL_ARRAY_SIZE(GPIO_GROUP)
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#define get_st_gpio(p) (GPIO_GROUP[PIN_BANK(p)])
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#define get_st_pin(p) (HAL_BIT(PIN_NUM(p)))
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[GPIO_BANK_NUM * PIN_NUMBER_PER_BANK];
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/********************* Private Function Definition ***************************/
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/** @defgroup GPIO_Private_Function Private Function
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* @{
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*/
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static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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if (pin < 0 || pin >= HAL_ARRAY_SIZE(pin_irq_hdr_tab))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[pin].pin == pin &&
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pin_irq_hdr_tab[pin].hdr == hdr &&
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pin_irq_hdr_tab[pin].mode == mode &&
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pin_irq_hdr_tab[pin].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[pin].pin != BANK_PIN_DEFAULT && pin_irq_hdr_tab[pin].hdr != RT_NULL)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[pin].pin = pin;
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pin_irq_hdr_tab[pin].hdr = hdr;
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pin_irq_hdr_tab[pin].mode = mode;
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pin_irq_hdr_tab[pin].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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if (pin < 0 || pin >= HAL_ARRAY_SIZE(pin_irq_hdr_tab))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[pin].pin == BANK_PIN_DEFAULT)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[pin].pin = BANK_PIN_DEFAULT;
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pin_irq_hdr_tab[pin].hdr = RT_NULL;
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pin_irq_hdr_tab[pin].mode = 0;
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pin_irq_hdr_tab[pin].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t pin_irq_enable(struct rt_device *dev, rt_base_t pin, rt_uint32_t enabled)
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{
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rt_base_t level;
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eGPIO_intType mode;
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RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
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if (enabled == PIN_IRQ_ENABLE)
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{
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if (pin < 0 || pin >= HAL_ARRAY_SIZE(pin_irq_hdr_tab))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[pin].pin == BANK_PIN_DEFAULT)
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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switch (pin_irq_hdr_tab[pin].mode)
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{
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case PIN_IRQ_MODE_RISING:
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mode = GPIO_INT_TYPE_EDGE_RISING;
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break;
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case PIN_IRQ_MODE_FALLING:
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mode = GPIO_INT_TYPE_EDGE_FALLING;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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mode = GPIO_INT_TYPE_EDGE_BOTH;
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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mode = GPIO_INT_TYPE_LEVEL_LOW;
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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mode = GPIO_INT_TYPE_LEVEL_HIGH;
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break;
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default:
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rt_hw_interrupt_enable(level);
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return RT_EINVAL;
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}
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HAL_GPIO_SetIntType(get_st_gpio(pin), get_st_pin(pin), mode);
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HAL_GPIO_EnableIRQ(get_st_gpio(pin), get_st_pin(pin));
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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HAL_GPIO_DisableIRQ(get_st_gpio(pin), get_st_pin(pin));
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}
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else
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{
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return RT_ENOSYS;
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}
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return RT_EOK;
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}
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static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
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{
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RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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case PIN_MODE_OUTPUT_OD:
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#ifdef HAL_PINCTRL_MODULE_ENABLED
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#ifdef RK_BSP_TEMP
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HAL_PINCTRL_SetIOMUX(PIN_BANK(pin), HAL_BIT(pin), PIN_CONFIG_MUX_FUNC0);
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#endif
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#endif
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HAL_GPIO_SetPinDirection(get_st_gpio(pin), get_st_pin(pin), GPIO_OUT);
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break;
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case PIN_MODE_INPUT:
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case PIN_MODE_INPUT_PULLUP:
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case PIN_MODE_INPUT_PULLDOWN:
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#ifdef HAL_PINCTRL_MODULE_ENABLED
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#ifdef RK_BSP_TEMP
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HAL_PINCTRL_SetIOMUX(PIN_BANK(pin), HAL_BIT(pin), PIN_CONFIG_MUX_FUNC0);
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#endif
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#endif
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HAL_GPIO_SetPinDirection(get_st_gpio(pin), get_st_pin(pin), GPIO_IN);
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break;
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default:
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break;
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}
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}
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static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
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{
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RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
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HAL_GPIO_SetPinLevel(get_st_gpio(pin), get_st_pin(pin), value);
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}
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static int pin_read(struct rt_device *dev, rt_base_t pin)
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{
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RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
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return HAL_GPIO_GetPinLevel(get_st_gpio(pin), get_st_pin(pin));;
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}
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/** @} */
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#ifdef GPIO0
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void pin_gpio0_handler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_IRQHandler(GPIO0, GPIO_BANK0);
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rt_interrupt_leave();
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}
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#endif
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#ifdef GPIO1
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void pin_gpio1_handler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_IRQHandler(GPIO1, GPIO_BANK1);
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rt_interrupt_leave();
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}
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#endif
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#ifdef GPIO2
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void pin_gpio2_handler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_IRQHandler(GPIO2, GPIO_BANK2);
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rt_interrupt_leave();
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}
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#endif
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#ifdef GPIO3
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void pin_gpio3_handler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_IRQHandler(GPIO3, GPIO_BANK3);
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rt_interrupt_leave();
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}
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#endif
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#ifdef GPIO4
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void pin_gpio4_handler(void)
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{
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rt_interrupt_enter();
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HAL_GPIO_IRQHandler(GPIO4, GPIO_BANK4);
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rt_interrupt_leave();
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}
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#endif
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static const struct rt_pin_ops pin_ops =
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{
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pin_mode,
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pin_write,
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pin_read,
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pin_attach_irq,
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pin_detach_irq,
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pin_irq_enable,
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};
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/** @defgroup GPIO_Public_Functions Public Functions
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* @{
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*/
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int rt_hw_gpio_init(void)
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{
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#ifdef GPIO0
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rt_hw_interrupt_install(GPIO0_IRQn, (void *)pin_gpio0_handler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(GPIO0_IRQn);
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#endif
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#ifdef GPIO1
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rt_hw_interrupt_install(GPIO1_IRQn, (void *)pin_gpio1_handler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(GPIO1_IRQn);
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#endif
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#ifdef GPIO2
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rt_hw_interrupt_install(GPIO2_IRQn, (void *)pin_gpio2_handler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(GPIO2_IRQn);
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#endif
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#ifdef GPIO3
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rt_hw_interrupt_install(GPIO3_IRQn, (void *)pin_gpio3_handler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(GPIO3_IRQn);
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#endif
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#ifdef GPIO4
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rt_hw_interrupt_install(GPIO4_IRQn, (void *)pin_gpio4_handler, RT_NULL, RT_NULL);
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rt_hw_interrupt_umask(GPIO4_IRQn);
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#endif
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rt_device_pin_register("pin", &pin_ops, RT_NULL);
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_gpio_init);
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/** @} */
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static void pin_irq_hdr(uint32_t pin)
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{
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RT_ASSERT(pin >= 0);
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RT_ASSERT(pin < HAL_ARRAY_SIZE(pin_irq_hdr_tab));
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RT_ASSERT(pin_irq_hdr_tab[pin].hdr != RT_NULL);
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pin_irq_hdr_tab[pin].hdr(pin_irq_hdr_tab[pin].args);
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}
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void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin)
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{
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RT_ASSERT(bank < GPIO_BANK_NUM);
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pin_irq_hdr(BANK_PIN(bank, pin));
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}
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#endif
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/** @} */
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/** @} */
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