582 lines
17 KiB
C
582 lines
17 KiB
C
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/*
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* @brief SPI master ROM API declarations and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "hw_spimd.h"
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#define DRVVERSION 0x0100
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/* Private callback for FIFO push and pop functions. This privately maps
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to the VFIFO for the SPI master, but can be overriden if needed. The driver will
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automatically pick the right implementation at run-time based on the transfer
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size in the transfer descriptor. */
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typedef uint16_t (*spiMasterFifoPushFN)(LPC_SPI_T *pSPI, void *data, uint32_t sendBytes, uint32_t curIndex);
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typedef uint16_t (*spiMasterFifoPopFN)(LPC_SPI_T *pSPI, void *data, uint32_t bytes, uint32_t curIndex);
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/* Private data structure used for the SPI master driver, holds the driver and
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peripheral context */
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typedef struct {
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void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
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LPC_SPI_T *base; /*!< Base address of SPI peripheral to use */
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uint32_t baseClockRate; /*!< SPI base clock rate in Hz, call Init() again if this rate changes */
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spiMasterXferCSAssertCB pAssertCb; /*!< SSEL assertion callback */
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spiMasterTransmitCB pTranCb; /*!< Transmit data start callback */
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spiMasterReceiveCB pRecvCb; /*!< Receive data start callback */
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spiMMasterXferCSDeAssertCB pDeassertCb; /*!< SSEL deassertion callback */
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spiMasterFifoPushFN pPushFN; /*!< Pointer to current FIFO push function */
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spiMasterFifoPopFN pPopFN; /*!< Pointer to current FIFO pop function */
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ROM_SPIM_XFER_T *pXfer; /*!< Pointer to current transfer descriptor */
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uint32_t sendIdx; /*!< Current transmit buffer index */
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uint32_t recvIdx; /*!< Current receive buffer index */
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ErrorCode_t pendingStatus; /*!< Pending transfer status */
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uint8_t xmitOn; /*!< Transfer in progress flag */
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uint8_t terminate; /*!< Terminate transfer flag */
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uint8_t reserved[2];
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} SPIM_DATACONTEXT_T;
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/* Maps config registers bits for SPI mode to the transfer descriptor */
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static const uint32_t spiModeBits[4] = {
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(SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST),
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(SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND),
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(SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST),
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(SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND)
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};
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void spim_close_pending_transfer(ROM_SPIM_HANDLE_T pHandle);
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/* FIFO push function using standard SPI FIFO for datum >8 bits */
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static uint16_t _rom_spimMasterFifoPush16(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex)
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{
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uint16_t pushed = 0, *p16 = (uint16_t *) data;
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/* Push as 16-bit value */
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while ((numData > 0) && ((pSPI->STAT & SPI_STAT_TXRDY) != 0)) {
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pSPI->TXDAT = (uint32_t) p16[curIndex];
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numData--;
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curIndex++;
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pushed++;
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}
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return pushed;
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}
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/* FIFO pop function using standard SPI FIFO for datum >8 bits */
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static uint16_t _rom_spimMasterFifoPop16(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex)
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{
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uint16_t popped = 0, *p16 = (uint16_t *) data;
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/* Pop as 16-bit value */
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while ((numData > 0) && ((pSPI->STAT & SPI_STAT_RXRDY) != 0)) {
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p16[curIndex] = (uint16_t) pSPI->RXDAT;
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numData--;
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curIndex++;
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popped++;
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}
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return popped;
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}
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/* FIFO push function using standard SPI FIFO for datum <=8 bits */
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static uint16_t _rom_spimMasterFifoPush8(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex)
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{
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uint16_t pushed = 0;
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uint8_t *p8 = (uint8_t *) data;
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/* Push as 8-bit value */
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while ((numData > 0) && ((pSPI->STAT & SPI_STAT_TXRDY) != 0)) {
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pSPI->TXDAT = (uint32_t) p8[curIndex];
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numData--;
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curIndex++;
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pushed++;
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}
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return pushed;
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}
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/* FIFO pop function using standard SPI FIFO for datum <=8 bits */
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static uint16_t _rom_spimMasterFifoPop8(LPC_SPI_T *pSPI, void *data, uint32_t numData, uint32_t curIndex)
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{
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uint16_t popped = 0;
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uint8_t *p8 = (uint8_t *) data;
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/* Pop as 16-bit value */
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while ((numData > 0) && ((pSPI->STAT & SPI_STAT_RXRDY) != 0)) {
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p8[curIndex] = (uint8_t) pSPI->RXDAT;
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numData--;
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curIndex++;
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popped++;
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}
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return popped;
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}
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/* Assert a SPI select */
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static void _rom_spimAssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum)
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{
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/* Assert a SSEL line by driving it low */
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pSPI->TXCTRL &= ~SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum);
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}
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static void _rom_spimCloseTransfer(SPIM_DATACONTEXT_T *pDrv)
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{
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/* Transfer terminates after this byte */
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pDrv->xmitOn = 0;
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pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN;
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}
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static void _rom_spimTransmitHandler(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer)
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{
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SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
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/* Is DMA being used? */
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if ((pXfer->flags & ROM_SPIM_FLAG_DMATX) != 0) {
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/* Call transmit callback, callback is pre-validated by setup */
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if (pDrv->pTranCb) {
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pDrv->pTranCb(pHandle, pXfer);
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pDrv->base->INTENCLR = SPI_INTENSET_TXDYEN;
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}
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}
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else { /* Transfer without using DMA */
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if ((pXfer->flags & ROM_SPIM_FLAG_TXIGNORE) != 0) {
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/* ROM_SPIM_FLAG_TXIGNORE flag is set. Will send 0xFF and decrement txSz,
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transfer terminates on last data */
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static const uint16_t sb = 0xFFFF;
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if (pDrv->sendIdx >= pXfer->txSz) {
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/* Transferring last datum, end transfer */
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spim_close_pending_transfer(pHandle);
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}
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else {
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if (pDrv->sendIdx >= (pXfer->txSz - 1)) {
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pDrv->base->TXCTRL |= SPI_TXCTL_EOT;
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}
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pDrv->sendIdx += pDrv->pPushFN(pDrv->base, (void *) &sb, 1, 0);
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}
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}
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else {
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/* Normal data transfer */
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if (pDrv->sendIdx >= pXfer->txSz) {
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/* Ran out of data, so stop */
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spim_close_pending_transfer(pHandle);
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}
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else {
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pDrv->sendIdx += pDrv->pPushFN(pDrv->base, (void *) pXfer->txBuff, 1, pDrv->sendIdx);
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/* Call callback for more data */
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if (pDrv->sendIdx >= pXfer->txSz) {
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if (pDrv->pTranCb) {
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pDrv->pTranCb(pHandle, pXfer);
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pDrv->sendIdx = 0;
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}
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else {
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/* No transmit callback, close transfer */
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spim_close_pending_transfer(pHandle);
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}
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}
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}
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}
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}
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}
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static void _rom_spimReceiveHandler(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer)
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{
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SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
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/* Is DMA being used? */
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if ((pXfer->flags & ROM_SPIM_FLAG_DMARX) != 0) {
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/* Call receive callback, callback is pre-validated by setup */
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if (pDrv->pRecvCb) {
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pDrv->pRecvCb(pHandle, pXfer);
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pDrv->base->INTENCLR = SPI_INTENSET_RXDYEN;
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}
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}
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else { /* Transfer without using DMA */
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/* Normal data transfer */
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if (pDrv->recvIdx >= pXfer->rxSz) {
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uint16_t temp;
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/* Ran out of data, overflowing */
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pDrv->pendingStatus = ERR_SPI_RXOVERRUN;
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pDrv->recvIdx += pDrv->pPopFN(pDrv->base, (void *) &temp, 1, 0); /* Flush data */
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}
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else {
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pDrv->recvIdx += pDrv->pPopFN(pDrv->base, (void *) pXfer->rxBuff, 1, pDrv->recvIdx);
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/* Call callback for more data */
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if ((pDrv->recvIdx >= pXfer->rxSz) && (pDrv->pRecvCb)) {
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pDrv->pRecvCb(pHandle, pXfer);
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pDrv->recvIdx = 0;
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}
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}
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}
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}
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// **********************************************************
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uint32_t spim_get_mem_size(void)
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{
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return sizeof(SPIM_DATACONTEXT_T);
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}
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ROM_SPIM_HANDLE_T spim_init(void *mem, const ROM_SPIM_INIT_T *pInit)
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{
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SPIM_DATACONTEXT_T *pDrv;
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int i;
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/* Verify alignment is at least 4 bytes and clock rate is not 0 */
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if ((((uint32_t) mem & 0x3) != 0) || (pInit->baseClockRate == 0)) {
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return NULL;
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}
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pDrv = (SPIM_DATACONTEXT_T *) mem;
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memset(pDrv, 0, sizeof(SPIM_DATACONTEXT_T));
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/* Save base of peripheral and pointer to user data */
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pDrv->pUserData = pInit->pUserData;
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pDrv->base = (LPC_SPI_T *) pInit->base;
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pDrv->baseClockRate = pInit->baseClockRate;
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/* Enable SPI master interface, deassert all chip selects */
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pDrv->base->CFG = 0;/* Forces state machine reset */
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pDrv->base->CFG = SPI_CFG_SPI_EN | SPI_CFG_MASTER_EN;
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/* Set SPI slave select (SSEL) polarity for each slave signal */
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for (i = 0; i <= 3; i++) {
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if (pInit->spiPol[i] == 0) {
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/* Active low select, high during idle */
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pDrv->base->CFG &= ~(1 << (8 + i));
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}
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else {
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/* Active high, low during idle */
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pDrv->base->CFG |= (1 << (8 + i));
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}
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}
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/* Deassert all chip selects */
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pDrv->base->TXCTRL = SPI_TXDATCTL_DEASSERT_ALL;
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/* Clear pending master statuses - RXOV, TXUR, SSA, SSD, EOT */
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pDrv->base->STAT = (SPI_STAT_RXOV | SPI_STAT_TXUR | SPI_STAT_SSA |
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SPI_STAT_SSD | SPI_STAT_EOT);
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return (ROM_SPIM_HANDLE_T) pDrv;
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}
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void spim_register_callback(ROM_SPIM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB)
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{
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SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
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switch (cbIndex) {
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case ROM_SPIM_ASSERTSSEL_CB:
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pDrv->pAssertCb = (spiMasterXferCSAssertCB) pCB;
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break;
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case ROM_SPIM_DATATRANSMIT_CB:
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pDrv->pTranCb = (spiMasterTransmitCB) pCB;
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break;
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case ROM_SPIM_DATATRECEIVE_CB:
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pDrv->pRecvCb = (spiMasterReceiveCB) pCB;
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break;
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case ROM_SPIM_DEASSERTSSEL_CB:
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pDrv->pDeassertCb = (spiMMasterXferCSDeAssertCB) pCB;
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break;
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}
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}
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ErrorCode_t spim_setup_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg)
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{
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SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
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uint32_t reg;
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/* Verify config is valid */
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if (pCfg == NULL) {
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return ERR_SPI_PARAM;
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}
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||
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/* Verify data parameters area valid */
|
||
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if ((pCfg->dataBits == 0) || (pCfg->dataBits > 16) || (pCfg->dXferBitRate == 0)) {
|
||
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return ERR_SPI_PARAM;
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}
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||
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||
|
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/* Verify mode */
|
||
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if (pCfg->mode > ROM_SPI_CLOCK_MODE3) {
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||
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return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Transfer timing is valid? */
|
||
|
|
if ((pCfg->PreDelay > 15) || (pCfg->PostDelay > 15) || (pCfg->FrameDelay > 15) ||
|
||
|
|
(pCfg->TransferDelay > 16)) {
|
||
|
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return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Compute real clock rate from desired clock rate */
|
||
|
|
reg = pDrv->baseClockRate / pCfg->dXferBitRate;
|
||
|
|
if ((pDrv->baseClockRate % pCfg->dXferBitRate) != 0) {
|
||
|
|
reg++;
|
||
|
|
}
|
||
|
|
if (reg > 0x10000) {
|
||
|
|
reg = 0x10000;
|
||
|
|
}
|
||
|
|
else if (reg == 0) {
|
||
|
|
reg = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Save pre-computed divider and set real SPI master bit rate for app */
|
||
|
|
pDrv->base->DIV = (reg - 1);
|
||
|
|
pCfg->rXferBitRate = pDrv->baseClockRate / reg;
|
||
|
|
|
||
|
|
/* Setup transfer timing */
|
||
|
|
if (pCfg->TransferDelay == 0) {
|
||
|
|
pCfg->TransferDelay = 1;
|
||
|
|
}
|
||
|
|
pDrv->base->DLY = (
|
||
|
|
SPI_DLY_PRE_DELAY(pCfg->PreDelay) |
|
||
|
|
SPI_DLY_POST_DELAY(pCfg->PostDelay) |
|
||
|
|
SPI_DLY_FRAME_DELAY(pCfg->FrameDelay) |
|
||
|
|
SPI_DLY_TRANSFER_DELAY(pCfg->TransferDelay - 1));
|
||
|
|
|
||
|
|
/* Setup transfer mode and LSB/MSB first */
|
||
|
|
reg = pDrv->base->CFG;
|
||
|
|
reg &= ~(SPI_CFG_LSB_FIRST_EN | SPI_CFG_CPHA_SECOND |
|
||
|
|
SPI_CFG_CPOL_HI);
|
||
|
|
|
||
|
|
/* Setup SPI transfer configuration (CFG register) */
|
||
|
|
reg |= spiModeBits[(int) pCfg->mode];
|
||
|
|
if (pCfg->lsbFirst) {
|
||
|
|
reg |= SPI_CFG_LSB_FIRST_EN;
|
||
|
|
}
|
||
|
|
pDrv->base->CFG = reg;
|
||
|
|
|
||
|
|
/* Setup SPI transfer configuration (TXCTRL) for data size, don't alter SPI SSEL states */
|
||
|
|
reg = pDrv->base->TXCTRL & ~SPI_TXCTL_FLEN(16);
|
||
|
|
if (pCfg->FrameDelay > 0) {
|
||
|
|
reg |= SPI_TXCTL_EOF;
|
||
|
|
}
|
||
|
|
pDrv->base->TXCTRL = reg | SPI_TXCTL_FLEN(pCfg->dataBits);
|
||
|
|
|
||
|
|
/* Setup FIFO callbacks based on the data transfer width */
|
||
|
|
if (pCfg->dataBits > 8) {
|
||
|
|
pDrv->pPushFN = &_rom_spimMasterFifoPush16;
|
||
|
|
pDrv->pPopFN = &_rom_spimMasterFifoPop16;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
pDrv->pPushFN = &_rom_spimMasterFifoPush8;
|
||
|
|
pDrv->pPopFN = &_rom_spimMasterFifoPop8;
|
||
|
|
}
|
||
|
|
|
||
|
|
return LPC_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
ErrorCode_t spim_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer)
|
||
|
|
{
|
||
|
|
SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
|
||
|
|
uint32_t reg;
|
||
|
|
uint8_t flen;
|
||
|
|
|
||
|
|
/* Get length of a receive value */
|
||
|
|
flen = 1 + (uint8_t) ((pDrv->base->TXCTRL >> 24) & 0xF);
|
||
|
|
|
||
|
|
/* Is transfer descriptor valid? */
|
||
|
|
if (pXfer == NULL) {
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Is slave select valid? */
|
||
|
|
if (pXfer->sselNum >= ROM_SPIM_MAXSELECTS) {
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Verify transmit size, must have at least 1 byte */
|
||
|
|
if (pXfer->txSz == 0) {
|
||
|
|
pXfer->status = ERR_SPI_INVALID_LENGTH;
|
||
|
|
return ERR_SPI_INVALID_LENGTH;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* No need to check RX buffer alignment if ROM_SPIM_FLAG_RXIGNORE flag is set */
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_RXIGNORE) == 0) {
|
||
|
|
if ((pXfer->rxSz == 0) || (pXfer->rxBuff == NULL)) {
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
if ((flen > 8) && ((((uint32_t) pXfer->rxBuff) & 0x1) != 0)) {
|
||
|
|
/* Receive buffer not 16-bit aligned or not present */
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
/* Is DMA being used? */
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_DMARX) != 0) {
|
||
|
|
if (pDrv->pRecvCb == NULL) {
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check transmit buffer alignment */
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_TXIGNORE) == 0) {
|
||
|
|
if ((pXfer->txSz == 0) || (pXfer->txBuff == NULL)) {
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
if ((flen > 8) && ((((uint32_t) pXfer->txBuff) & 0x1) != 0)) {
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
/* Is DMA being used? */
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_DMATX) != 0) {
|
||
|
|
if (pDrv->pTranCb == NULL) {
|
||
|
|
pXfer->status = ERR_SPI_PARAM;
|
||
|
|
return ERR_SPI_PARAM;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If in loopback mode, set loopback enable */
|
||
|
|
reg = pDrv->base->CFG;
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_LOOPBACK) != 0) {
|
||
|
|
reg |= SPI_CFG_LBM_EN;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
reg &= ~SPI_CFG_LBM_EN;
|
||
|
|
}
|
||
|
|
pDrv->base->CFG = reg;
|
||
|
|
|
||
|
|
/* ROM_SPIM_FLAG_RXIGNORE flag */
|
||
|
|
reg = pDrv->base->TXCTRL & ~SPI_TXCTL_EOT;
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_RXIGNORE) != 0) {
|
||
|
|
reg |= SPI_TXCTL_RXIGNORE;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
reg &= ~SPI_TXCTL_RXIGNORE;
|
||
|
|
}
|
||
|
|
pDrv->base->TXCTRL = reg;
|
||
|
|
|
||
|
|
/* Save pointer to transfer descriptor and initial status */
|
||
|
|
pDrv->pXfer = pXfer;
|
||
|
|
pXfer->status = ERR_SPI_BUSY;
|
||
|
|
pDrv->pendingStatus = LPC_OK;
|
||
|
|
pDrv->sendIdx = pDrv->recvIdx = 0;
|
||
|
|
|
||
|
|
/* Transmit start, no terminate */
|
||
|
|
pDrv->xmitOn = 1;
|
||
|
|
pDrv->terminate = 0;
|
||
|
|
|
||
|
|
/* Start transfer by asserting selected slave */
|
||
|
|
_rom_spimAssertSSEL(pDrv->base, pXfer->sselNum);
|
||
|
|
|
||
|
|
/* Enable SPI interrupts for master */
|
||
|
|
pDrv->base->INTENSET = SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN |
|
||
|
|
SPI_INTENSET_SSAEN | SPI_INTENSET_SSDEN;
|
||
|
|
|
||
|
|
/* Is transfer blocking? */
|
||
|
|
if ((pXfer->flags & ROM_SPIM_FLAG_BLOCKING) != 0) {
|
||
|
|
while (pXfer->status == ERR_SPI_BUSY) {
|
||
|
|
spim_transfer_handler(pHandle);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return pXfer->status;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Otime = "optimize for speed of code execution"
|
||
|
|
// ...add this pragma 1 line above the interrupt service routine function.
|
||
|
|
void spim_transfer_handler(ROM_SPIM_HANDLE_T pHandle)
|
||
|
|
{
|
||
|
|
SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
|
||
|
|
ROM_SPIM_XFER_T *pXfer = pDrv->pXfer;
|
||
|
|
uint32_t status = pDrv->base->STAT;
|
||
|
|
|
||
|
|
/* Master asserts slave */
|
||
|
|
if ((status & SPI_STAT_SSA) != 0) {
|
||
|
|
pDrv->base->STAT = SPI_STAT_SSA;
|
||
|
|
pDrv->base->INTENCLR = SPI_INTENSET_SSAEN;
|
||
|
|
|
||
|
|
/* Master SSEL assertion callback */
|
||
|
|
if (pDrv->pAssertCb != NULL) {
|
||
|
|
pDrv->pAssertCb(pHandle, pXfer);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Transmit data handler */
|
||
|
|
if (((status & SPI_STAT_TXRDY) != 0) && (pDrv->xmitOn == 1)) {
|
||
|
|
/* Handle transmit */
|
||
|
|
_rom_spimTransmitHandler(pHandle, pXfer);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Receive data handler */
|
||
|
|
if ((status & SPI_STAT_RXRDY) != 0) {
|
||
|
|
/* Handle receive */
|
||
|
|
_rom_spimReceiveHandler(pHandle, pXfer);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If the controller is stalled and the transmit is finished, close the transfer
|
||
|
|
or be stuck in a stalled condition indefinitely. */
|
||
|
|
if (((status & SPI_STAT_STALLED) != 0) && (pDrv->xmitOn == 0)) {
|
||
|
|
spim_close_pending_transfer(pHandle);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Master SSEL de-assertion callback */
|
||
|
|
if ((status & SPI_STAT_SSD) != 0) {
|
||
|
|
pDrv->base->STAT = SPI_STAT_SSD;
|
||
|
|
pDrv->base->INTENCLR = SPI_INTENSET_SSAEN | SPI_INTENSET_SSDEN |
|
||
|
|
SPI_INTENSET_RXDYEN | SPI_INTENSET_TXDYEN;
|
||
|
|
pXfer->status = pDrv->pendingStatus;
|
||
|
|
|
||
|
|
/* De-assetion event */
|
||
|
|
if (pDrv->pDeassertCb != NULL) {
|
||
|
|
pDrv->pDeassertCb(pHandle, pXfer);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void spim_close_pending_transfer(ROM_SPIM_HANDLE_T pHandle)
|
||
|
|
{
|
||
|
|
SPIM_DATACONTEXT_T *pDrv = (SPIM_DATACONTEXT_T *) pHandle;
|
||
|
|
|
||
|
|
/* If stalled, force an EOT */
|
||
|
|
if ((pDrv->base->STAT & SPI_STAT_STALLED) != 0) {
|
||
|
|
pDrv->base->STAT = SPI_STAT_EOT;
|
||
|
|
}
|
||
|
|
pDrv->base->TXCTRL |= SPI_TXCTL_EOT;
|
||
|
|
|
||
|
|
_rom_spimCloseTransfer(pDrv);
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t spim_get_driver_version(void)
|
||
|
|
{
|
||
|
|
return DRVVERSION;
|
||
|
|
}
|
||
|
|
|
||
|
|
// *********************************************************
|