474 lines
17 KiB
ArmAsm
474 lines
17 KiB
ArmAsm
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;/*****************************************************************************
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; * @file: startup_LPC54114_cm0plus.s
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; * @purpose: CMSIS Cortex-M0 Core Device Startup File
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; * LPC54114_cm0plus
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; * @version: 1.0
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; * @date: 2016-4-29
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; *----------------------------------------------------------------------------
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; *
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; * The Clear BSD License
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; * Copyright 1997 - 2016 Freescale Semiconductor.
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; * Copyright 2016 - 2017 NXP
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; *
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; * All rights reserved.
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; *
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; Redistribution and use in source and binary forms, with or without modification,
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; are permitted (subject to the limitations in the disclaimer below) provided
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; that the following conditions are met:
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;
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; o Redistributions of source code must retain the above copyright notice, this list
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; of conditions and the following disclaimer.
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;
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; o Redistributions in binary form must reproduce the above copyright notice, this
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; list of conditions and the following disclaimer in the documentation and/or
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; other materials provided with the distribution.
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;
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; o Neither the name of the copyright holder nor the names of its
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; contributors may be used to endorse or promote products derived from this
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; software without specific prior written permission.
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;
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; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S' PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD 0
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DCD 0
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DCD 0
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD 0
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DCD 0
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect
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DCD DMA0_IRQHandler ; DMA controller
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DCD GINT0_IRQHandler ; GPIO group 0
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DCD GINT1_IRQHandler ; GPIO group 1
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DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0
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DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1
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DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2
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DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3
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DCD UTICK0_IRQHandler ; Micro-tick Timer
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DCD MRT0_IRQHandler ; Multi-rate timer
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DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0
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DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1
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DCD SCT0_IRQHandler ; SCTimer/PWM
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DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3
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DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C)
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DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C)
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DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C)
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DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C)
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DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C)
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DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C)
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DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S)
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DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S)
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DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion.
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DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion.
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DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error.
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DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem
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DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector
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DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt
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DCD USB0_IRQHandler ; USB device
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DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts
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DCD IOH_IRQHandler ; IOH
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DCD MAILBOX_IRQHandler ; Mailbox interrupt (present on selected devices)
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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#if !defined(SLAVEBOOT)
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DATA
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cpu_id EQU 0xE000ED00 ; CPUID Base Register (System control block register)
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cpu_ctrl EQU 0x40000800
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coproc_boot EQU 0x40000804
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coproc_stack EQU 0x40000808
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rel_vals
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DC32 cpu_id, cpu_ctrl, coproc_boot, coproc_stack
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DC16 0xFFF, 0xC24
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#endif
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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; Reset Handler - shared for both cores
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Reset_Handler
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#if !defined(SLAVEBOOT)
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; Both the M0+ and M4 core come via this shared startup code,
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; but the M0+ and M4 core have different vector tables.
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; Determine if the core executing this code is the master or
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; the slave and handle each core state individually.
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shared_boot_entry
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LDR r6, =rel_vals
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MOVS r4, #0 ; Flag for slave core (0)
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MOVS r5, #1
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; Determine which core (M0+ or M4) this code is running on
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; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
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get_current_core_id
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LDR r0, [r6, #0]
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LDR r1, [r0] ; r1 = CPU ID status
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LSRS r1, r1, #4 ; Right justify 12 CPU ID bits
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LDRH r2, [r6, #16] ; Mask for CPU ID bits
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ANDS r2, r1, r2 ; r2 = ARM COrtex CPU ID
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LDRH r3, [r6, #18] ; Mask for CPU ID bits
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CMP r3, r2 ; Core ID matches M4 identifier
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BNE get_master_status
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MOV r4, r5 ; Set flag for master core (1)
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; Determine if M4 core is the master or slave
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; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
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get_master_status
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LDR r0, [r6, #4]
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LDR r3, [r0] ; r3 = SYSCON co-processor CPU control status
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ANDS r3, r3, r5 ; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
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; Select boot based on selected master core and core ID
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select_boot
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EORS r3, r3, r4 ; r4 = (Bit 0: 0 = master, 1 = slave)
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BNE slave_boot
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B normal_boot
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; Slave boot
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slave_boot
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LDR r0, [r6, #8]
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LDR r2, [r0] ; r1 = SYSCON co-processor boot address
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CMP r2, #0 ; Slave boot address = 0 (not set up)?
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BEQ cpu_sleep
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LDR r0, [r6, #12]
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LDR r1, [r0] ; r5 = SYSCON co-processor stack address
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MOV sp, r1 ; Update slave CPU stack pointer
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; Be sure to update VTOR for the slave MCU to point to the
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; slave vector table in boot memory
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BX r2 ; Jump to slave boot address
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; Slave isn't yet setup for system boot from the master
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; so sleep until the master sets it up and then reboots it
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cpu_sleep
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MOV sp, r5 ; Will force exception if something happens
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cpu_sleep_wfi
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WFI ; Sleep forever until master reboots
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B cpu_sleep_wfi
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#endif ; defined(SLAVEBOOT)
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; Normal boot for master/slave
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normal_boot
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LDR r0, =SystemInit
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BLX r0
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LDR r0, =__iar_program_start
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BX r0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B .
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B .
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B .
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B .
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B .
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|
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PUBWEAK WDT_BOD_IRQHandler
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PUBWEAK WDT_BOD_DriverIRQHandler
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SECTION .text:CODE:REORDER:NOROOT(2)
|
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WDT_BOD_IRQHandler
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||
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LDR R0, =WDT_BOD_DriverIRQHandler
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BX R0
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PUBWEAK DMA0_IRQHandler
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||
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PUBWEAK DMA0_DriverIRQHandler
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||
|
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SECTION .text:CODE:REORDER:NOROOT(2)
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DMA0_IRQHandler
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|
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LDR R0, =DMA0_DriverIRQHandler
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BX R0
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PUBWEAK GINT0_IRQHandler
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PUBWEAK GINT0_DriverIRQHandler
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||
|
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SECTION .text:CODE:REORDER:NOROOT(2)
|
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|
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GINT0_IRQHandler
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||
|
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LDR R0, =GINT0_DriverIRQHandler
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|
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BX R0
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||
|
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PUBWEAK GINT1_IRQHandler
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||
|
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PUBWEAK GINT1_DriverIRQHandler
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||
|
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SECTION .text:CODE:REORDER:NOROOT(2)
|
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|
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GINT1_IRQHandler
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||
|
|
LDR R0, =GINT1_DriverIRQHandler
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|
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BX R0
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||
|
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PUBWEAK PIN_INT0_IRQHandler
|
||
|
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PUBWEAK PIN_INT0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
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PIN_INT0_IRQHandler
|
||
|
|
LDR R0, =PIN_INT0_DriverIRQHandler
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||
|
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BX R0
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||
|
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PUBWEAK PIN_INT1_IRQHandler
|
||
|
|
PUBWEAK PIN_INT1_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
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PIN_INT1_IRQHandler
|
||
|
|
LDR R0, =PIN_INT1_DriverIRQHandler
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||
|
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BX R0
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||
|
|
PUBWEAK PIN_INT2_IRQHandler
|
||
|
|
PUBWEAK PIN_INT2_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
PIN_INT2_IRQHandler
|
||
|
|
LDR R0, =PIN_INT2_DriverIRQHandler
|
||
|
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BX R0
|
||
|
|
PUBWEAK PIN_INT3_IRQHandler
|
||
|
|
PUBWEAK PIN_INT3_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
PIN_INT3_IRQHandler
|
||
|
|
LDR R0, =PIN_INT3_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK UTICK0_IRQHandler
|
||
|
|
PUBWEAK UTICK0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
UTICK0_IRQHandler
|
||
|
|
LDR R0, =UTICK0_DriverIRQHandler
|
||
|
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BX R0
|
||
|
|
PUBWEAK MRT0_IRQHandler
|
||
|
|
PUBWEAK MRT0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
MRT0_IRQHandler
|
||
|
|
LDR R0, =MRT0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK CTIMER0_IRQHandler
|
||
|
|
PUBWEAK CTIMER0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
CTIMER0_IRQHandler
|
||
|
|
LDR R0, =CTIMER0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK CTIMER1_IRQHandler
|
||
|
|
PUBWEAK CTIMER1_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
CTIMER1_IRQHandler
|
||
|
|
LDR R0, =CTIMER1_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK SCT0_IRQHandler
|
||
|
|
PUBWEAK SCT0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
SCT0_IRQHandler
|
||
|
|
LDR R0, =SCT0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK CTIMER3_IRQHandler
|
||
|
|
PUBWEAK CTIMER3_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
CTIMER3_IRQHandler
|
||
|
|
LDR R0, =CTIMER3_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM0_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM0_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM1_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM1_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM1_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM1_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM2_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM2_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM2_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM2_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM3_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM3_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM3_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM3_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM4_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM4_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM4_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM4_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM5_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM5_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM5_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM5_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM6_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM6_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM6_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM6_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK FLEXCOMM7_IRQHandler
|
||
|
|
PUBWEAK FLEXCOMM7_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
FLEXCOMM7_IRQHandler
|
||
|
|
LDR R0, =FLEXCOMM7_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK ADC0_SEQA_IRQHandler
|
||
|
|
PUBWEAK ADC0_SEQA_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
ADC0_SEQA_IRQHandler
|
||
|
|
LDR R0, =ADC0_SEQA_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK ADC0_SEQB_IRQHandler
|
||
|
|
PUBWEAK ADC0_SEQB_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
ADC0_SEQB_IRQHandler
|
||
|
|
LDR R0, =ADC0_SEQB_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK ADC0_THCMP_IRQHandler
|
||
|
|
PUBWEAK ADC0_THCMP_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
ADC0_THCMP_IRQHandler
|
||
|
|
LDR R0, =ADC0_THCMP_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK DMIC0_IRQHandler
|
||
|
|
PUBWEAK DMIC0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
DMIC0_IRQHandler
|
||
|
|
LDR R0, =DMIC0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK HWVAD0_IRQHandler
|
||
|
|
PUBWEAK HWVAD0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
HWVAD0_IRQHandler
|
||
|
|
LDR R0, =HWVAD0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK USB0_NEEDCLK_IRQHandler
|
||
|
|
PUBWEAK USB0_NEEDCLK_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
USB0_NEEDCLK_IRQHandler
|
||
|
|
LDR R0, =USB0_NEEDCLK_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK USB0_IRQHandler
|
||
|
|
PUBWEAK USB0_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
USB0_IRQHandler
|
||
|
|
LDR R0, =USB0_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK RTC_IRQHandler
|
||
|
|
PUBWEAK RTC_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
RTC_IRQHandler
|
||
|
|
LDR R0, =RTC_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK IOH_IRQHandler
|
||
|
|
PUBWEAK IOH_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
IOH_IRQHandler
|
||
|
|
LDR R0, =IOH_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
PUBWEAK MAILBOX_IRQHandler
|
||
|
|
PUBWEAK MAILBOX_DriverIRQHandler
|
||
|
|
SECTION .text:CODE:REORDER:NOROOT(2)
|
||
|
|
MAILBOX_IRQHandler
|
||
|
|
LDR R0, =MAILBOX_DriverIRQHandler
|
||
|
|
BX R0
|
||
|
|
WDT_BOD_DriverIRQHandler
|
||
|
|
DMA0_DriverIRQHandler
|
||
|
|
GINT0_DriverIRQHandler
|
||
|
|
GINT1_DriverIRQHandler
|
||
|
|
PIN_INT0_DriverIRQHandler
|
||
|
|
PIN_INT1_DriverIRQHandler
|
||
|
|
PIN_INT2_DriverIRQHandler
|
||
|
|
PIN_INT3_DriverIRQHandler
|
||
|
|
UTICK0_DriverIRQHandler
|
||
|
|
MRT0_DriverIRQHandler
|
||
|
|
CTIMER0_DriverIRQHandler
|
||
|
|
CTIMER1_DriverIRQHandler
|
||
|
|
SCT0_DriverIRQHandler
|
||
|
|
CTIMER3_DriverIRQHandler
|
||
|
|
FLEXCOMM0_DriverIRQHandler
|
||
|
|
FLEXCOMM1_DriverIRQHandler
|
||
|
|
FLEXCOMM2_DriverIRQHandler
|
||
|
|
FLEXCOMM3_DriverIRQHandler
|
||
|
|
FLEXCOMM4_DriverIRQHandler
|
||
|
|
FLEXCOMM5_DriverIRQHandler
|
||
|
|
FLEXCOMM6_DriverIRQHandler
|
||
|
|
FLEXCOMM7_DriverIRQHandler
|
||
|
|
ADC0_SEQA_DriverIRQHandler
|
||
|
|
ADC0_SEQB_DriverIRQHandler
|
||
|
|
ADC0_THCMP_DriverIRQHandler
|
||
|
|
DMIC0_DriverIRQHandler
|
||
|
|
HWVAD0_DriverIRQHandler
|
||
|
|
USB0_NEEDCLK_DriverIRQHandler
|
||
|
|
USB0_DriverIRQHandler
|
||
|
|
RTC_DriverIRQHandler
|
||
|
|
IOH_DriverIRQHandler
|
||
|
|
MAILBOX_DriverIRQHandler
|
||
|
|
DefaultISR
|
||
|
|
B .
|
||
|
|
|
||
|
|
END
|