271 lines
8.4 KiB
C
271 lines
8.4 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_usart.h"
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#include "fsl_device_registers.h"
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#include "fsl_dma.h"
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#include "fsl_flexcomm.h"
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#include "fsl_usart_dma.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma"
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#endif
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/*<! Structure definition for uart_dma_handle_t. The structure is private. */
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typedef struct _usart_dma_private_handle
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{
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USART_Type *base;
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usart_dma_handle_t *handle;
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} usart_dma_private_handle_t;
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enum _usart_transfer_states
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{
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kUSART_TxIdle, /* TX idle. */
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kUSART_TxBusy, /* TX busy. */
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kUSART_RxIdle, /* RX idle. */
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kUSART_RxBusy /* RX busy. */
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};
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/*<! Private handle only used for internally. */
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static usart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_USART_COUNT];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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static void USART_TransferSendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
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{
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assert(handle);
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assert(param);
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usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
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/* Disable UART TX DMA. */
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USART_EnableTxDMA(usartPrivateHandle->base, false);
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usartPrivateHandle->handle->txState = kUSART_TxIdle;
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if (usartPrivateHandle->handle->callback)
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{
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usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle,
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usartPrivateHandle->handle->userData);
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}
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}
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static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
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{
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assert(handle);
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assert(param);
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usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
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/* Disable UART RX DMA. */
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USART_EnableRxDMA(usartPrivateHandle->base, false);
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usartPrivateHandle->handle->rxState = kUSART_RxIdle;
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if (usartPrivateHandle->handle->callback)
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{
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usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle,
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usartPrivateHandle->handle->userData);
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}
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}
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status_t USART_TransferCreateHandleDMA(USART_Type *base,
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usart_dma_handle_t *handle,
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usart_dma_transfer_callback_t callback,
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void *userData,
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dma_handle_t *txDmaHandle,
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dma_handle_t *rxDmaHandle)
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{
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int32_t instance = 0;
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/* check 'base' */
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assert(!(NULL == base));
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if (NULL == base)
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{
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return kStatus_InvalidArgument;
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}
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/* check 'handle' */
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assert(!(NULL == handle));
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if (NULL == handle)
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{
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return kStatus_InvalidArgument;
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}
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instance = USART_GetInstance(base);
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memset(handle, 0, sizeof(*handle));
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/* assign 'base' and 'handle' */
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s_dmaPrivateHandle[instance].base = base;
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s_dmaPrivateHandle[instance].handle = handle;
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/* set tx/rx 'idle' state */
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handle->rxState = kUSART_RxIdle;
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handle->txState = kUSART_TxIdle;
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handle->callback = callback;
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handle->userData = userData;
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handle->rxDmaHandle = rxDmaHandle;
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handle->txDmaHandle = txDmaHandle;
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/* Configure TX. */
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if (txDmaHandle)
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{
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DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
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}
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/* Configure RX. */
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if (rxDmaHandle)
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{
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DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
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}
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return kStatus_Success;
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}
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status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
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{
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assert(handle);
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assert(handle->txDmaHandle);
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assert(xfer);
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assert(xfer->data);
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assert(xfer->dataSize);
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dma_transfer_config_t xferConfig;
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status_t status;
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/* If previous TX not finished. */
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if (kUSART_TxBusy == handle->txState)
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{
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status = kStatus_USART_TxBusy;
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}
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else
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{
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handle->txState = kUSART_TxBusy;
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handle->txDataSizeAll = xfer->dataSize;
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/* Enable DMA request from txFIFO */
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USART_EnableTxDMA(base, true);
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/* Prepare transfer. */
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DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t),
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xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
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/* Submit transfer. */
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DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
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DMA_StartTransfer(handle->txDmaHandle);
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status = kStatus_Success;
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}
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return status;
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}
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status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
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{
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assert(handle);
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assert(handle->rxDmaHandle);
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assert(xfer);
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assert(xfer->data);
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assert(xfer->dataSize);
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dma_transfer_config_t xferConfig;
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status_t status;
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/* If previous RX not finished. */
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if (kUSART_RxBusy == handle->rxState)
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{
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status = kStatus_USART_RxBusy;
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}
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else
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{
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handle->rxState = kUSART_RxBusy;
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handle->rxDataSizeAll = xfer->dataSize;
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/* Enable DMA request from rxFIFO */
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USART_EnableRxDMA(base, true);
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/* Prepare transfer. */
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DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t),
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xfer->dataSize, kDMA_PeripheralToMemory, NULL);
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/* Submit transfer. */
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DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
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DMA_StartTransfer(handle->rxDmaHandle);
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status = kStatus_Success;
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}
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return status;
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}
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void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle)
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{
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assert(NULL != handle);
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assert(NULL != handle->txDmaHandle);
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/* Stop transfer. */
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DMA_AbortTransfer(handle->txDmaHandle);
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handle->txState = kUSART_TxIdle;
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}
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void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle)
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{
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assert(NULL != handle);
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assert(NULL != handle->rxDmaHandle);
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/* Stop transfer. */
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DMA_AbortTransfer(handle->rxDmaHandle);
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handle->rxState = kUSART_RxIdle;
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}
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status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count)
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{
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assert(handle);
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assert(handle->rxDmaHandle);
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assert(count);
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if (kUSART_RxIdle == handle->rxState)
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{
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return kStatus_NoTransferInProgress;
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}
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*count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
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return kStatus_Success;
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}
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