527 lines
19 KiB
C
527 lines
19 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_spi_dma.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma"
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#endif
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/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
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typedef struct _spi_dma_private_handle
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{
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SPI_Type *base;
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spi_dma_handle_t *handle;
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} spi_dma_private_handle_t;
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/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
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enum _spi_dma_states_t
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{
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kSPI_Idle = 0x0, /*!< SPI is idle state */
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kSPI_Busy /*!< SPI is busy tranferring data. */
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};
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typedef struct _spi_dma_txdummy
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{
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uint32_t lastWord;
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uint32_t word;
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} spi_dma_txdummy_t;
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/*<! Private handle only used for internally. */
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static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief DMA callback function for SPI send transfer.
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*
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* @param handle DMA handle pointer.
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* @param userData User data for DMA callback function.
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*/
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static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
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/*!
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* @brief DMA callback function for SPI receive transfer.
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*
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* @param handle DMA handle pointer.
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* @param userData User data for DMA callback function.
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*/
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static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if defined(__ICCARM__)
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#pragma data_alignment = 4
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static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
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#elif defined(__CC_ARM)
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__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
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#elif defined(__GNUC__)
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__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
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#endif
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#if defined(__ICCARM__)
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#pragma data_alignment = 4
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static uint16_t s_rxDummy;
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static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT];
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#elif defined(__CC_ARM)
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__attribute__((aligned(4))) static uint16_t s_rxDummy;
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__attribute__((aligned(4))) static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT];
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#elif defined(__GNUC__)
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__attribute__((aligned(4))) static uint16_t s_rxDummy;
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__attribute__((aligned(4))) static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT];
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#endif
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#if defined(__ICCARM__)
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#pragma data_alignment = 16
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static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
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#elif defined(__CC_ARM)
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__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
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#elif defined(__GNUC__)
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__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void XferToFifoWR(spi_transfer_t *xfer, uint32_t *fifowr)
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{
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*fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0;
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*fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0;
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}
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static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr)
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{
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*fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum)));
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/* set width of data - range asserted at entry */
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*fifowr |= SPI_FIFOWR_LEN(config->dataWidth);
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}
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static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config)
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{
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if (config->dataWidth > kSPI_Data8Bits)
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{
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*txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2]));
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}
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else
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{
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*txLastWord = xfer->txData[xfer->dataSize - 1];
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}
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XferToFifoWR(xfer, txLastWord);
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SpiConfigToFifoWR(config, txLastWord);
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}
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static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
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{
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uint32_t instance = SPI_GetInstance(base);
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dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]);
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dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]);
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XferToFifoWR(xfer, &dummy->word);
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XferToFifoWR(xfer, &dummy->lastWord);
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SpiConfigToFifoWR(spi_config_p, &dummy->word);
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SpiConfigToFifoWR(spi_config_p, &dummy->lastWord);
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/* Clear the end of transfer bit for continue word transfer. */
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dummy->word &= (uint32_t)(~kSPI_FrameAssert);
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}
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status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
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spi_dma_handle_t *handle,
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spi_dma_callback_t callback,
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void *userData,
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dma_handle_t *txHandle,
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dma_handle_t *rxHandle)
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{
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int32_t instance = 0;
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/* check 'base' */
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assert(!(NULL == base));
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if (NULL == base)
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{
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return kStatus_InvalidArgument;
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}
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/* check 'handle' */
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assert(!(NULL == handle));
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if (NULL == handle)
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{
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return kStatus_InvalidArgument;
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}
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instance = SPI_GetInstance(base);
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memset(handle, 0, sizeof(*handle));
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/* Set spi base to handle */
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handle->txHandle = txHandle;
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handle->rxHandle = rxHandle;
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handle->callback = callback;
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handle->userData = userData;
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/* Set SPI state to idle */
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handle->state = kSPI_Idle;
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/* Set handle to global state */
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s_dmaPrivateHandle[instance].base = base;
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s_dmaPrivateHandle[instance].handle = handle;
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/* Install callback for Tx dma channel */
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DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
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DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
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return kStatus_Success;
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}
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status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
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{
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int32_t instance;
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status_t result = kStatus_Success;
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spi_config_t *spi_config_p;
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assert(!((NULL == handle) || (NULL == xfer)));
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if ((NULL == handle) || (NULL == xfer))
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{
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return kStatus_InvalidArgument;
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}
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/* Byte size is zero. */
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assert(!(xfer->dataSize == 0));
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if (xfer->dataSize == 0)
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{
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return kStatus_InvalidArgument;
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}
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/* cannot get instance from base address */
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instance = SPI_GetInstance(base);
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assert(!(instance < 0));
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if (instance < 0)
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{
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return kStatus_InvalidArgument;
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}
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/* Check if the device is busy */
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if (handle->state == kSPI_Busy)
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{
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return kStatus_SPI_Busy;
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}
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else
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{
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uint32_t tmp;
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dma_transfer_config_t xferConfig = {0};
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spi_config_p = (spi_config_t *)SPI_GetConfig(base);
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handle->state = kStatus_SPI_Busy;
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handle->transferSize = xfer->dataSize;
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/* receive */
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SPI_EnableRxDMA(base, true);
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if (xfer->rxData)
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{
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DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData,
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
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xfer->dataSize, kDMA_PeripheralToMemory, NULL);
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}
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else
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{
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DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy,
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
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xfer->dataSize, kDMA_StaticToStatic, NULL);
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}
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DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
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handle->rxInProgress = true;
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DMA_StartTransfer(handle->rxHandle);
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/* transmit */
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SPI_EnableTxDMA(base, true);
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if (xfer->configFlags & kSPI_FrameAssert)
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{
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PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p);
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}
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if (xfer->txData)
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{
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/* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma
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* descriptor to send the last data.
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*/
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if ((xfer->configFlags & kSPI_FrameAssert) &&
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
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{
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dma_xfercfg_t tmp_xfercfg = {0};
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tmp_xfercfg.valid = true;
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tmp_xfercfg.swtrig = true;
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tmp_xfercfg.intA = true;
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tmp_xfercfg.byteWidth = sizeof(uint32_t);
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tmp_xfercfg.srcInc = 0;
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tmp_xfercfg.dstInc = 0;
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tmp_xfercfg.transferCount = 1;
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/* Create chained descriptor to transmit last word */
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DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance],
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((void *)((uint32_t)&base->FIFOWR)), NULL);
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DMA_PrepareTransfer(
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&xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)),
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)),
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kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]);
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/* Disable interrupts for first descriptor to avoid calling callback twice. */
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xferConfig.xfercfg.intA = false;
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xferConfig.xfercfg.intB = false;
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result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
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if (result != kStatus_Success)
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{
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return result;
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}
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}
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else
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{
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DMA_PrepareTransfer(
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&xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)),
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
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xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
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DMA_SubmitTransfer(handle->txHandle, &xferConfig);
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}
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}
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else
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{
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/* Setup tx dummy data. */
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SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p);
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if ((xfer->configFlags & kSPI_FrameAssert) &&
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((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
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{
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dma_xfercfg_t tmp_xfercfg = {0};
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tmp_xfercfg.valid = true;
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tmp_xfercfg.swtrig = true;
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tmp_xfercfg.intA = true;
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tmp_xfercfg.byteWidth = sizeof(uint32_t);
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tmp_xfercfg.srcInc = 0;
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tmp_xfercfg.dstInc = 0;
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tmp_xfercfg.transferCount = 1;
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/* Create chained descriptor to transmit last word */
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DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
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(void *)((uint32_t)&base->FIFOWR), NULL);
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/* Use common API to setup first descriptor */
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DMA_PrepareTransfer(
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&xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)),
|
||
|
|
((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||
|
|
((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)),
|
||
|
|
kDMA_StaticToStatic, &s_spi_descriptor_table[instance]);
|
||
|
|
/* Disable interrupts for first descriptor to avoid calling callback twice */
|
||
|
|
xferConfig.xfercfg.intA = false;
|
||
|
|
xferConfig.xfercfg.intB = false;
|
||
|
|
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
|
||
|
|
if (result != kStatus_Success)
|
||
|
|
{
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
DMA_PrepareTransfer(
|
||
|
|
&xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)),
|
||
|
|
((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||
|
|
xfer->dataSize, kDMA_StaticToStatic, NULL);
|
||
|
|
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
|
||
|
|
if (result != kStatus_Success)
|
||
|
|
{
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
handle->txInProgress = true;
|
||
|
|
tmp = 0;
|
||
|
|
XferToFifoWR(xfer, &tmp);
|
||
|
|
SpiConfigToFifoWR(spi_config_p, &tmp);
|
||
|
|
|
||
|
|
/* Setup the control info.
|
||
|
|
* Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO.
|
||
|
|
* And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR
|
||
|
|
* will push the data and the current control bits into the FIFO.
|
||
|
|
*/
|
||
|
|
if ((xfer->configFlags & kSPI_FrameAssert) &&
|
||
|
|
((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U)))
|
||
|
|
{
|
||
|
|
*(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */
|
||
|
|
tmp &= (uint32_t)(~kSPI_FrameAssert);
|
||
|
|
*(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U);
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_StartTransfer(handle->txHandle);
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer)
|
||
|
|
{
|
||
|
|
assert(xfer);
|
||
|
|
assert(handle);
|
||
|
|
spi_transfer_t tempXfer = {0};
|
||
|
|
status_t status;
|
||
|
|
|
||
|
|
if (xfer->isTransmitFirst)
|
||
|
|
{
|
||
|
|
tempXfer.txData = xfer->txData;
|
||
|
|
tempXfer.rxData = NULL;
|
||
|
|
tempXfer.dataSize = xfer->txDataSize;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
tempXfer.txData = NULL;
|
||
|
|
tempXfer.rxData = xfer->rxData;
|
||
|
|
tempXfer.dataSize = xfer->rxDataSize;
|
||
|
|
}
|
||
|
|
/* If the pcs pin keep assert between transmit and receive. */
|
||
|
|
if (xfer->isPcsAssertInTransfer)
|
||
|
|
{
|
||
|
|
tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert;
|
||
|
|
}
|
||
|
|
|
||
|
|
status = SPI_MasterTransferBlocking(base, &tempXfer);
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (xfer->isTransmitFirst)
|
||
|
|
{
|
||
|
|
tempXfer.txData = NULL;
|
||
|
|
tempXfer.rxData = xfer->rxData;
|
||
|
|
tempXfer.dataSize = xfer->rxDataSize;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
tempXfer.txData = xfer->txData;
|
||
|
|
tempXfer.rxData = NULL;
|
||
|
|
tempXfer.dataSize = xfer->txDataSize;
|
||
|
|
}
|
||
|
|
tempXfer.configFlags = xfer->configFlags;
|
||
|
|
|
||
|
|
status = SPI_MasterTransferDMA(base, handle, &tempXfer);
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
|
||
|
|
{
|
||
|
|
spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
|
||
|
|
spi_dma_handle_t *spiHandle = privHandle->handle;
|
||
|
|
SPI_Type *base = privHandle->base;
|
||
|
|
|
||
|
|
/* change the state */
|
||
|
|
spiHandle->rxInProgress = false;
|
||
|
|
|
||
|
|
/* All finished, call the callback */
|
||
|
|
if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
|
||
|
|
{
|
||
|
|
spiHandle->state = kSPI_Idle;
|
||
|
|
if (spiHandle->callback)
|
||
|
|
{
|
||
|
|
(spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
|
||
|
|
{
|
||
|
|
spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
|
||
|
|
spi_dma_handle_t *spiHandle = privHandle->handle;
|
||
|
|
SPI_Type *base = privHandle->base;
|
||
|
|
|
||
|
|
/* change the state */
|
||
|
|
spiHandle->txInProgress = false;
|
||
|
|
|
||
|
|
/* All finished, call the callback */
|
||
|
|
if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
|
||
|
|
{
|
||
|
|
spiHandle->state = kSPI_Idle;
|
||
|
|
if (spiHandle->callback)
|
||
|
|
{
|
||
|
|
(spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
|
||
|
|
{
|
||
|
|
assert(NULL != handle);
|
||
|
|
|
||
|
|
/* Stop tx transfer first */
|
||
|
|
DMA_AbortTransfer(handle->txHandle);
|
||
|
|
/* Then rx transfer */
|
||
|
|
DMA_AbortTransfer(handle->rxHandle);
|
||
|
|
|
||
|
|
/* Set the handle state */
|
||
|
|
handle->txInProgress = false;
|
||
|
|
handle->rxInProgress = false;
|
||
|
|
handle->state = kSPI_Idle;
|
||
|
|
}
|
||
|
|
|
||
|
|
status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
|
||
|
|
{
|
||
|
|
assert(handle);
|
||
|
|
|
||
|
|
if (!count)
|
||
|
|
{
|
||
|
|
return kStatus_InvalidArgument;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Catch when there is not an active transfer. */
|
||
|
|
if (handle->state != kSPI_Busy)
|
||
|
|
{
|
||
|
|
*count = 0;
|
||
|
|
return kStatus_NoTransferInProgress;
|
||
|
|
}
|
||
|
|
|
||
|
|
size_t bytes;
|
||
|
|
|
||
|
|
bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
|
||
|
|
|
||
|
|
*count = handle->transferSize - bytes;
|
||
|
|
|
||
|
|
return kStatus_Success;
|
||
|
|
}
|