560 lines
20 KiB
C
560 lines
20 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_sctimer.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.sctimer"
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#endif
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/*! @brief Typedef for interrupt handler. */
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typedef void (*sctimer_isr_t)(SCT_Type *base);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base SCTimer peripheral base address
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*
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* @return The SCTimer instance
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*/
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static uint32_t SCTIMER_GetInstance(SCT_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to SCT bases for each instance. */
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static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to SCT clocks for each instance. */
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static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET
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/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */
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static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N;
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#else
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/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */
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static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
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#endif
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/*!< @brief SCTimer event Callback function. */
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static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
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/*!< @brief Keep track of SCTimer event number */
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static uint32_t s_currentEvent;
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/*!< @brief Keep track of SCTimer state number */
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static uint32_t s_currentState;
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/*!< @brief Keep track of SCTimer match/capture register number */
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static uint32_t s_currentMatch;
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/*! @brief Pointer to SCTimer IRQ handler */
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static sctimer_isr_t s_sctimerIsr;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t SCTIMER_GetInstance(SCT_Type *base)
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{
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uint32_t instance;
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uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < sctArrayCount; instance++)
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{
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if (s_sctBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < sctArrayCount);
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return instance;
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}
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status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
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{
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assert(config);
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uint32_t i;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the SCTimer clock*/
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CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset the module */
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RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
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/* Setup the counter operation */
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base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
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SCT_CONFIG_UNIFY(config->enableCounterUnify);
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/* Write to the control register, clear the counter and keep the counters halted */
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base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) |
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SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK;
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if (!(config->enableCounterUnify))
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{
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base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) |
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SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK;
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}
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/* Initial state of channel output */
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base->OUTPUT = config->outInitState;
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/* Clear the global variables */
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s_currentEvent = 0;
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s_currentState = 0;
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s_currentMatch = 0;
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/* Clear the callback array */
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for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
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{
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s_eventCallback[i] = NULL;
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}
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/* Save interrupt handler */
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s_sctimerIsr = SCTIMER_EventHandleIRQ;
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return kStatus_Success;
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}
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void SCTIMER_Deinit(SCT_Type *base)
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{
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/* Halt the counters */
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base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the SCTimer clock*/
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CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
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{
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assert(config);
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/* SCT operates as a unified 32-bit counter */
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config->enableCounterUnify = true;
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/* System clock clocks the entire SCT module */
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config->clockMode = kSCTIMER_System_ClockMode;
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/* This is used only by certain clock modes */
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config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
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/* Up count mode only for the unified counter */
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config->enableBidirection_l = false;
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/* Up count mode only for Counte_H */
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config->enableBidirection_h = false;
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/* Prescale factor of 1 */
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config->prescale_l = 0;
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/* Prescale factor of 1 for Counter_H*/
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config->prescale_h = 0;
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/* Clear outputs */
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config->outInitState = 0;
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}
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status_t SCTIMER_SetupPwm(SCT_Type *base,
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const sctimer_pwm_signal_param_t *pwmParams,
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sctimer_pwm_mode_t mode,
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uint32_t pwmFreq_Hz,
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uint32_t srcClock_Hz,
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uint32_t *event)
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{
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assert(pwmParams);
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assert(srcClock_Hz);
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assert(pwmFreq_Hz);
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assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS);
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uint32_t period, pulsePeriod = 0;
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uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1);
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uint32_t periodEvent = 0, pulseEvent = 0;
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uint32_t reg;
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/* This function will create 2 events, return an error if we do not have enough events available */
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if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
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{
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return kStatus_Fail;
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}
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if (pwmParams->dutyCyclePercent == 0)
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{
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return kStatus_Fail;
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}
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/* Set unify bit to operate in 32-bit counter mode */
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base->CONFIG |= SCT_CONFIG_UNIFY_MASK;
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/* Use bi-directional mode for center-aligned PWM */
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if (mode == kSCTIMER_CenterAlignedPwm)
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{
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base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
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}
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/* Calculate PWM period match value */
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if (mode == kSCTIMER_EdgeAlignedPwm)
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{
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period = (sctClock / pwmFreq_Hz) - 1;
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}
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else
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{
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period = sctClock / (pwmFreq_Hz * 2);
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}
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/* Calculate pulse width match value */
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pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100;
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/* For 100% dutycyle, make pulse period greater than period so the event will never occur */
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if (pwmParams->dutyCyclePercent >= 100)
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{
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pulsePeriod = period + 2;
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}
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/* Schedule an event when we reach the PWM period */
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SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent);
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/* Schedule an event when we reach the pulse width */
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SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent);
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/* Reset the counter when we reach the PWM period */
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SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent);
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/* Return the period event to the user */
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*event = periodEvent;
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/* For high-true level */
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if (pwmParams->level == kSCTIMER_HighTrue)
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{
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/* Set the initial output level to low which is the inactive state */
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base->OUTPUT &= ~(1U << pwmParams->output);
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if (mode == kSCTIMER_EdgeAlignedPwm)
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{
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/* Set the output when we reach the PWM period */
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SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent);
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/* Clear the output when we reach the PWM pulse value */
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SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
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}
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else
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{
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/* Clear the output when we reach the PWM pulse event */
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SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
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/* Reverse output when down counting */
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reg = base->OUTPUTDIRCTRL;
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reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
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reg |= (1U << (2 * pwmParams->output));
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base->OUTPUTDIRCTRL = reg;
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}
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}
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/* For low-true level */
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else
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{
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/* Set the initial output level to high which is the inactive state */
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base->OUTPUT |= (1U << pwmParams->output);
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if (mode == kSCTIMER_EdgeAlignedPwm)
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{
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/* Clear the output when we reach the PWM period */
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SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent);
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/* Set the output when we reach the PWM pulse value */
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SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
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}
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else
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{
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/* Set the output when we reach the PWM pulse event */
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SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
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/* Reverse output when down counting */
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reg = base->OUTPUTDIRCTRL;
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reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
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reg |= (1U << (2 * pwmParams->output));
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base->OUTPUTDIRCTRL = reg;
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}
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}
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return kStatus_Success;
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}
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void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
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{
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assert(dutyCyclePercent > 0);
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assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS);
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uint32_t periodMatchReg, pulseMatchReg;
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uint32_t pulsePeriod = 0, period;
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/* Retrieve the match register number for the PWM period */
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periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
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/* Retrieve the match register number for the PWM pulse period */
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pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
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period = base->SCTMATCH[periodMatchReg];
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/* Calculate pulse width match value */
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pulsePeriod = (period * dutyCyclePercent) / 100;
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/* For 100% dutycyle, make pulse period greater than period so the event will never occur */
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if (dutyCyclePercent >= 100)
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{
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pulsePeriod = period + 2;
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}
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/* Stop the counter before updating match register */
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SCTIMER_StopTimer(base, kSCTIMER_Counter_L);
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/* Update dutycycle */
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base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod);
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base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod);
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/* Restart the counter */
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SCTIMER_StartTimer(base, kSCTIMER_Counter_L);
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}
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|
||
|
|
status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
|
||
|
|
sctimer_event_t howToMonitor,
|
||
|
|
uint32_t matchValue,
|
||
|
|
uint32_t whichIO,
|
||
|
|
sctimer_counter_t whichCounter,
|
||
|
|
uint32_t *event)
|
||
|
|
{
|
||
|
|
uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT);
|
||
|
|
uint32_t currentCtrlVal = howToMonitor;
|
||
|
|
|
||
|
|
/* Return an error if we have hit the limit in terms of number of events created */
|
||
|
|
if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
|
||
|
|
{
|
||
|
|
return kStatus_Fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* IO only mode */
|
||
|
|
if (combMode == 0x2U)
|
||
|
|
{
|
||
|
|
base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO);
|
||
|
|
}
|
||
|
|
/* Match mode only */
|
||
|
|
else if (combMode == 0x1U)
|
||
|
|
{
|
||
|
|
/* Return an error if we have hit the limit in terms of number of number of match registers */
|
||
|
|
if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
||
|
|
{
|
||
|
|
return kStatus_Fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch);
|
||
|
|
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||
|
|
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||
|
|
{
|
||
|
|
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
|
||
|
|
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Select the counter, no need for this if operating in 32-bit mode */
|
||
|
|
currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
|
||
|
|
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
|
||
|
|
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
|
||
|
|
}
|
||
|
|
base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
|
||
|
|
/* Increment the match register number */
|
||
|
|
s_currentMatch++;
|
||
|
|
}
|
||
|
|
/* Use both Match & IO */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Return an error if we have hit the limit in terms of number of number of match registers */
|
||
|
|
if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
||
|
|
{
|
||
|
|
return kStatus_Fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO);
|
||
|
|
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||
|
|
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||
|
|
{
|
||
|
|
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
|
||
|
|
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Select the counter, no need for this if operating in 32-bit mode */
|
||
|
|
currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
|
||
|
|
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
|
||
|
|
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
|
||
|
|
}
|
||
|
|
base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
|
||
|
|
/* Increment the match register number */
|
||
|
|
s_currentMatch++;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable the event in the current state */
|
||
|
|
base->EVENT[s_currentEvent].STATE = (1U << s_currentState);
|
||
|
|
|
||
|
|
/* Return the event number */
|
||
|
|
*event = s_currentEvent;
|
||
|
|
|
||
|
|
/* Increment the event number */
|
||
|
|
s_currentEvent++;
|
||
|
|
|
||
|
|
return kStatus_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
|
||
|
|
{
|
||
|
|
/* Enable event in the current state */
|
||
|
|
base->EVENT[event].STATE |= (1U << s_currentState);
|
||
|
|
}
|
||
|
|
|
||
|
|
status_t SCTIMER_IncreaseState(SCT_Type *base)
|
||
|
|
{
|
||
|
|
/* Return an error if we have hit the limit in terms of states used */
|
||
|
|
if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES)
|
||
|
|
{
|
||
|
|
return kStatus_Fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
s_currentState++;
|
||
|
|
|
||
|
|
return kStatus_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
|
||
|
|
{
|
||
|
|
return s_currentState;
|
||
|
|
}
|
||
|
|
|
||
|
|
void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
|
||
|
|
{
|
||
|
|
assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS);
|
||
|
|
|
||
|
|
uint32_t reg;
|
||
|
|
|
||
|
|
/* Set the same event to set and clear the output */
|
||
|
|
base->OUT[whichIO].CLR |= (1U << event);
|
||
|
|
base->OUT[whichIO].SET |= (1U << event);
|
||
|
|
|
||
|
|
/* Set the conflict resolution to toggle output */
|
||
|
|
reg = base->RES;
|
||
|
|
reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO));
|
||
|
|
reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO));
|
||
|
|
base->RES = reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
|
||
|
|
sctimer_counter_t whichCounter,
|
||
|
|
uint32_t *captureRegister,
|
||
|
|
uint32_t event)
|
||
|
|
{
|
||
|
|
/* Return an error if we have hit the limit in terms of number of capture/match registers used */
|
||
|
|
if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
||
|
|
{
|
||
|
|
return kStatus_Fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||
|
|
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||
|
|
{
|
||
|
|
/* Set the bit to enable event */
|
||
|
|
base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event);
|
||
|
|
|
||
|
|
/* Set this resource to be a capture rather than match */
|
||
|
|
base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Set bit to enable event */
|
||
|
|
base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event);
|
||
|
|
|
||
|
|
/* Set this resource to be a capture rather than match */
|
||
|
|
base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return the match register number */
|
||
|
|
*captureRegister = s_currentMatch;
|
||
|
|
|
||
|
|
/* Increase the match register number */
|
||
|
|
s_currentMatch++;
|
||
|
|
|
||
|
|
return kStatus_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
|
||
|
|
{
|
||
|
|
s_eventCallback[event] = callback;
|
||
|
|
}
|
||
|
|
|
||
|
|
void SCTIMER_EventHandleIRQ(SCT_Type *base)
|
||
|
|
{
|
||
|
|
uint32_t eventFlag = SCT0->EVFLAG;
|
||
|
|
/* Only clear the flags whose interrupt field is enabled */
|
||
|
|
uint32_t clearFlag = (eventFlag & SCT0->EVEN);
|
||
|
|
uint32_t mask = eventFlag;
|
||
|
|
int i = 0;
|
||
|
|
|
||
|
|
/* Invoke the callback for certain events */
|
||
|
|
for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++)
|
||
|
|
{
|
||
|
|
if (mask & 0x1)
|
||
|
|
{
|
||
|
|
if (s_eventCallback[i] != NULL)
|
||
|
|
{
|
||
|
|
s_eventCallback[i]();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
mask >>= 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Clear event interrupt flag */
|
||
|
|
SCT0->EVFLAG = clearFlag;
|
||
|
|
}
|
||
|
|
|
||
|
|
void SCT0_IRQHandler(void)
|
||
|
|
{
|
||
|
|
s_sctimerIsr(SCT0);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|