327 lines
9.6 KiB
C
327 lines
9.6 KiB
C
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/*
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* Copyright (c) 2006-2021, Synwit Technology Co.,Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-07-01 lik first version
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*/
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#include "drv_adc.h"
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#ifdef RT_USING_ADC
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#ifdef BSP_USING_ADC
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//#define DRV_DEBUG
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#define LOG_TAG "drv.adc"
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#include <drv_log.h>
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#if !defined(BSP_USING_ADC0) && !defined(BSP_USING_ADC1)
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#error "Please define at least one BSP_USING_ADCx"
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/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
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#endif
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#ifdef BSP_USING_ADC0
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#ifndef ADC0_CFG
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#define ADC0_CFG \
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{ \
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.name = "adc0", \
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.ADCx = ADC0, \
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.ADC_initstruct.clk_src = ADC_CLKSRC_HRC_DIV8, \
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.ADC_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
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.ADC_initstruct.EOC_IEn = 0, \
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.ADC_initstruct.HalfIEn = 0, \
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.ADC_SEQ_initstruct.trig_src = ADC_TRIGGER_SW, \
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.ADC_SEQ_initstruct.conv_cnt = 1, \
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.ADC_SEQ_initstruct.samp_tim = ADC_SAMPLE_1CLOCK, \
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}
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#endif /* ADC0_CFG */
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#endif /* BSP_USING_ADC0 */
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CFG
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#define ADC1_CFG \
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{ \
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.name = "adc1", \
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.ADCx = ADC1, \
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.ADC_initstruct.clk_src = ADC_CLKSRC_HRC_DIV8, \
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.ADC_initstruct.samplAvg = ADC_AVG_SAMPLE1, \
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.ADC_initstruct.EOC_IEn = 0, \
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.ADC_initstruct.HalfIEn = 0, \
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.ADC_SEQ_initstruct.trig_src = ADC_TRIGGER_SW, \
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.ADC_SEQ_initstruct.conv_cnt = 1, \
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.ADC_SEQ_initstruct.samp_tim = ADC_SAMPLE_1CLOCK, \
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}
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#endif /* ADC1_CFG */
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#endif /* BSP_USING_ADC1 */
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struct swm_adc_cfg
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{
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const char *name;
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ADC_TypeDef *ADCx;
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ADC_InitStructure ADC_initstruct;
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ADC_SEQ_InitStructure ADC_SEQ_initstruct;
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};
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struct swm_adc_device
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{
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struct swm_adc_cfg *adc_cfg;
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struct rt_adc_device adc_device;
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};
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static struct swm_adc_cfg swm_adc_cfg[] =
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{
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#ifdef BSP_USING_ADC0
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ADC0_CFG,
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#endif
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#ifdef BSP_USING_ADC1
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ADC1_CFG,
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#endif
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};
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static struct swm_adc_device adc_obj[sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0])];
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static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel)
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{
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rt_uint32_t swm_channel = 0;
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switch (channel)
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{
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case 0:
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swm_channel = ADC_CH0;
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break;
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case 1:
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swm_channel = ADC_CH1;
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break;
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case 2:
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swm_channel = ADC_CH2;
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break;
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case 3:
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swm_channel = ADC_CH3;
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break;
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case 4:
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swm_channel = ADC_CH4;
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break;
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case 5:
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swm_channel = ADC_CH5;
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break;
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case 6:
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swm_channel = ADC_CH6;
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break;
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case 7:
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swm_channel = ADC_CH7;
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break;
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case 8:
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swm_channel = ADC_CH8;
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break;
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case 9:
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swm_channel = ADC_CH9;
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break;
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case 10:
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swm_channel = ADC_CH10;
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break;
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case 11:
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swm_channel = ADC_CH11;
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break;
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}
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return swm_channel;
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}
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static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled)
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{
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uint32_t adc_chn;
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struct swm_adc_cfg *adc_cfg;
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RT_ASSERT(adc_device != RT_NULL);
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adc_cfg = adc_device->parent.user_data;
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if (channel < 12)
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{
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/* set swm ADC channel */
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adc_chn = swm_adc_get_channel(channel);
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}
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else
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{
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LOG_E("ADC channel must be between 0 and 11.");
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return -RT_ERROR;
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}
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if (enabled)
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{
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adc_cfg->ADCx->SEQCHN0 |= adc_chn;
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}
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else
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{
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adc_cfg->ADCx->SEQCHN0 &= ~adc_chn;
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}
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return RT_EOK;
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}
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static rt_err_t swm_adc_convert(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value)
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{
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uint32_t i, chn, val, adc_chn;
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struct swm_adc_cfg *adc_cfg;
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RT_ASSERT(adc_device != RT_NULL);
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RT_ASSERT(value != RT_NULL);
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adc_cfg = adc_device->parent.user_data;
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if (channel < 12)
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{
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/* set swm ADC channel */
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adc_chn = swm_adc_get_channel(channel);
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}
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else
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{
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LOG_E("ADC channel must be between 0 and 11.");
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return -RT_ERROR;
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}
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*value = 0xFFFFFFFF;
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/* start ADC */
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ADC_Start(adc_cfg->ADCx, ADC_SEQ0);
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/* Wait for the ADC to convert */
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while (adc_cfg->ADCx->GO & ADC_GO_BUSY_Msk)
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__NOP();
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while ((adc_cfg->ADCx->SEQ[0].SR & ADC_SR_EMPTY_Msk) == 0)
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{
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val = ADC_Read(adc_cfg->ADCx, ADC_SEQ0, &chn);
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if (chn == adc_chn)
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{
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*value = val;
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}
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}
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if (*value == 0xFFFFFFFF)
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{
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LOG_E("ADC channel can not find.");
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static const struct rt_adc_ops swm_adc_ops =
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{
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.enabled = swm_adc_enabled,
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.convert = swm_adc_convert,
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};
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int swm_adc_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(swm_adc_cfg) / sizeof(swm_adc_cfg[0]); i++)
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{
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/* ADC init */
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adc_obj[i].adc_cfg = &swm_adc_cfg[i];
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if (adc_obj[i].adc_cfg->ADCx == ADC0)
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{
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#ifdef BSP_USING_ADC0_CHN0
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH0;
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PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC0_CH0, 0); //PC.6 => ADC.CH0
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#endif
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#ifdef BSP_USING_ADC0_CHN1
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH1;
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PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC0_CH1, 0); //PC.5 => ADC.CH1
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#endif
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#ifdef BSP_USING_ADC0_CHN2
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH2;
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PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC0_CH2, 0); //PC.4 => ADC.CH2
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#endif
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#ifdef BSP_USING_ADC0_CHN3
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH3;
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PORT_Init(PORTC, PIN3, PORTC_PIN3_ADC0_CH3, 0); //PC.3 => ADC.CH3
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#endif
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#ifdef BSP_USING_ADC0_CHN4
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH4;
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PORT_Init(PORTC, PIN2, PORTC_PIN2_ADC0_CH4, 0); //PC.2 => ADC.CH4
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#endif
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#ifdef BSP_USING_ADC0_CHN5
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH5;
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PORT_Init(PORTC, PIN1, PORTC_PIN1_ADC0_CH5, 0); //PC.1 => ADC.CH5
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#endif
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#ifdef BSP_USING_ADC0_CHN6
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH6;
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PORT_Init(PORTC, PIN0, PORTC_PIN0_ADC0_CH6, 0); //PC.0 => ADC.CH6
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#endif
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#ifdef BSP_USING_ADC0_CHN7
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH7;
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PORT_Init(PORTA, PIN15, PORTA_PIN15_ADC0_CH7, 0); //PA.15 => ADC.CH7
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#endif
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#ifdef BSP_USING_ADC0_CHN8
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH8;
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PORT_Init(PORTA, PIN14, PORTA_PIN14_ADC0_CH8, 0); //PA.14 => ADC.CH8
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#endif
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#ifdef BSP_USING_ADC0_CHN9
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH9;
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PORT_Init(PORTA, PIN13, PORTA_PIN13_ADC0_CH9, 0); //PA.13 => ADC.CH9
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#endif
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#ifdef BSP_USING_ADC0_CHN10
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH10;
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PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_CH10, 0); //PA.12 => ADC.CH10
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#endif
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#ifdef BSP_USING_ADC0_CHN11
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH11;
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PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_CH11, 0); //PA.10 => ADC.CH11
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#endif
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}
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else if (adc_obj[i].adc_cfg->ADCx == ADC1)
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{
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#ifdef BSP_USING_ADC1_CHN0
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH0;
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PORT_Init(PORTD, PIN1, PORTD_PIN1_ADC1_CH0, 0); //PD.1 => ADC1.CH0
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#endif
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#ifdef BSP_USING_ADC1_CHN1
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH1;
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PORT_Init(PORTD, PIN0, PORTD_PIN0_ADC1_CH1, 0); //PD.0 => ADC1.CH1
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#endif
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#ifdef BSP_USING_ADC1_CHN2
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH2;
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PORT_Init(PORTC, PIN13, PORTC_PIN13_ADC1_CH2, 0); //PC.13 => ADC1.CH2
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#endif
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#ifdef BSP_USING_ADC1_CHN3
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH3;
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PORT_Init(PORTC, PIN12, PORTC_PIN12_ADC1_CH3, 0); //PC.12 => ADC1.CH3
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#endif
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#ifdef BSP_USING_ADC1_CHN4
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH4;
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PORT_Init(PORTC, PIN11, PORTC_PIN11_ADC1_CH4, 0); //PC.11 => ADC1.CH4
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#endif
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#ifdef BSP_USING_ADC1_CHN5
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH5;
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PORT_Init(PORTC, PIN10, PORTC_PIN10_ADC1_CH5, 0); //PC.10 => ADC1.CH5
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#endif
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#ifdef BSP_USING_ADC1_CHN6
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adc_obj[i].adc_cfg->ADC_SEQ_initstruct.channels |= ADC_CH6;
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PORT_Init(PORTC, PIN9, PORTC_PIN9_ADC1_CH6, 0); //PC.9 => ADC1.CH6
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#endif
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}
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ADC_Init(adc_obj[i].adc_cfg->ADCx, &(adc_obj[i].adc_cfg->ADC_initstruct));
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ADC_SEQ_Init(adc_obj[i].adc_cfg->ADCx, ADC_SEQ0, &(adc_obj[i].adc_cfg->ADC_SEQ_initstruct));
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ADC_Open(adc_obj[i].adc_cfg->ADCx);
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ADC_Calibrate(adc_obj[i].adc_cfg->ADCx);
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result = rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].adc_cfg->name, &swm_adc_ops, adc_obj[i].adc_cfg);
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if(result != RT_EOK)
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{
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LOG_E("%s register fail.", adc_obj[i].adc_cfg->name);
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}
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else
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{
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LOG_D("%s register success.", adc_obj[i].adc_cfg->name);
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(swm_adc_init);
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#endif /* BSP_USING_ADC */
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#endif /* RT_USING_ADC */
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