2017-09-15 18:10:51 +08:00
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//*****************************************************************************
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//
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// am_hal_clkgen.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the CLKGEN.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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2018-09-21 16:10:44 +08:00
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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2017-09-15 18:10:51 +08:00
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//
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//*****************************************************************************
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#ifndef AM_HAL_CLKGEN_H
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#define AM_HAL_CLKGEN_H
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//*****************************************************************************
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//
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//! @name System Clock max frequency
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//! @brief Defines the maximum clock frequency for this device.
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//!
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//! These macros provide a definition of the maximum clock frequency.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CLKGEN_FREQ_MAX_HZ 48000000
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#define AM_HAL_CLKGEN_FREQ_MAX_MHZ (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000)
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//! @}
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//*****************************************************************************
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//
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//! @name System Clock Selection
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//! @brief Divisor selection for the main system clock.
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//!
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//! These macros may be used along with the am_hal_clkgen_sysctl_select()
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//! function to select the frequency of the main system clock.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CLKGEN_SYSCLK_MAX AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
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#define AM_HAL_CLKGEN_SYSCLK_48MHZ AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
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//! @}
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//*****************************************************************************
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//
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//! @name Interrupt Status Bits
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//! @brief Interrupt Status Bits for enable/disble use
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//!
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//! These macros may be used to set and clear interrupt bits.
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CLKGEN_INT_ALM AM_REG_CLKGEN_INTEN_ALM_M
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#define AM_HAL_CLKGEN_INT_OF AM_REG_CLKGEN_INTEN_OF_M
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#define AM_HAL_CLKGEN_INT_ACC AM_REG_CLKGEN_INTEN_ACC_M
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#define AM_HAL_CLKGEN_INT_ACF AM_REG_CLKGEN_INTEN_ACF_M
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//! @}
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//*****************************************************************************
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//
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//! @name OSC Start and Stop
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//! @brief OSC Start and Stop defines.
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//!
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//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x().
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CLKGEN_OSC_LFRC AM_REG_CLKGEN_OCTRL_STOPRC_M
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#define AM_HAL_CLKGEN_OSC_XT AM_REG_CLKGEN_OCTRL_STOPXT_M
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//! @}
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//*****************************************************************************
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//
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// OSC Start, Stop, Select defines
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//
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//*****************************************************************************
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV4 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV16 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_RTC_100Hz AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_100Hz
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2M AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT AM_REG_CLKGEN_CLKOUT_CKSEL_XT
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CG_100Hz AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLK AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLK
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FLASH_CLK AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV256 AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8K AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV64K AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FCLKNE AM_REG_CLKGEN_CLKOUT_CKSEL_FCLKNE
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#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE
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//*****************************************************************************
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//
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// UARTEN
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//
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//*****************************************************************************
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#define AM_HAL_CLKGEN_UARTEN_DIS AM_REG_CLKGEN_UARTEN_UART0EN_DIS
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#define AM_HAL_CLKGEN_UARTEN_EN AM_REG_CLKGEN_UARTEN_UART0EN_EN
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#define AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ
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#define AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV
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#define AM_HAL_CLKGEN_UARTEN_UARTENn_S(module) \
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((module) * \
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(AM_REG_CLKGEN_UARTEN_UART1EN_S - AM_REG_CLKGEN_UARTEN_UART0EN_S))
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#define AM_HAL_CLKGEN_UARTEN_UARTENn_M(module) \
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(AM_REG_CLKGEN_UARTEN_UART0EN_M << AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
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//
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// UARTEN: entype is one of DIS, EN, REDUCE_FREQ, EN_POWER_SAV.
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//
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#define AM_HAL_CLKGEN_UARTEN_UARTENn(module, entype) \
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(AM_REG_CLKGEN_UARTEN_UART0EN_##entype << \
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AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
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2018-09-21 16:10:44 +08:00
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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2017-09-15 18:10:51 +08:00
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//*****************************************************************************
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//
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// External function definitions
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//
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//*****************************************************************************
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extern void am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting);
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extern uint32_t am_hal_clkgen_sysclk_get(void);
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extern void am_hal_clkgen_osc_start(uint32_t ui32OscFlags);
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extern void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags);
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extern void am_hal_clkgen_clkout_enable(uint32_t ui32Signal);
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extern void am_hal_clkgen_clkout_disable(void);
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extern void am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn);
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extern void am_hal_clkgen_int_enable(uint32_t ui32Interrupt);
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extern uint32_t am_hal_clkgen_int_enable_get(void);
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extern void am_hal_clkgen_int_disable(uint32_t ui32Interrupt);
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extern void am_hal_clkgen_int_clear(uint32_t ui32Interrupt);
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extern void am_hal_clkgen_int_set(uint32_t ui32Interrupt);
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extern uint32_t am_hal_clkgen_int_status_get(bool bEnabledOnly);
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extern void am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency);
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extern void am_hal_clkgen_hfrc_adjust_disable(void);
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#ifdef __cplusplus
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}
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#endif
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#endif // AM_HAL_CLKGEN_H
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