563 lines
20 KiB
C
563 lines
20 KiB
C
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/*!
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\file gd32e230_dma.c
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\brief DMA driver
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\version 2018-06-19, V1.0.0, firmware for GD32E230
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32e230_dma.h"
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/*!
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\brief deinitialize DMA a channel registers
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\param[in] channelx: specify which DMA channel is deinitialized
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_deinit(dma_channel_enum channelx)
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{
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/* disable DMA a channel */
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
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/* reset DMA channel registers */
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DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
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DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
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DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
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DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
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DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
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}
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/*!
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\brief initialize the parameters of DMA struct with the default values
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\param[in] init_struct: the initialization data needed to initialize DMA channel
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\param[out] none
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\retval none
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*/
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void dma_struct_para_init(dma_parameter_struct* init_struct)
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{
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/* set the DMA struct with the default values */
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init_struct->periph_addr = 0U;
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init_struct->periph_width = 0U;
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init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE;
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init_struct->memory_addr = 0U;
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init_struct->memory_width = 0U;
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init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE;
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init_struct->number = 0U;
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init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY;
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init_struct->priority = (uint32_t)DMA_PRIORITY_LOW;
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}
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/*!
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\brief initialize DMA channel
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\param[in] channelx: specify which DMA channel is initialized
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] init_struct: the data needed to initialize DMA channel
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periph_addr: peripheral base address
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periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT
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periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE
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memory_addr: memory base address
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memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT
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memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
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direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL
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number: the number of remaining data to be transferred by the DMA
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priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
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\param[out] none
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\retval none
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*/
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void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct)
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{
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uint32_t ctl;
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dma_channel_disable(channelx);
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/* configure peripheral base address */
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DMA_CHPADDR(channelx) = init_struct->periph_addr;
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/* configure memory base address */
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DMA_CHMADDR(channelx) = init_struct->memory_addr;
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/* configure the number of remaining data to be transferred */
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DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
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/* configure peripheral transfer width,memory transfer width,channel priotity */
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ctl = DMA_CHCTL(channelx);
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ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
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ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
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DMA_CHCTL(channelx) = ctl;
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/* configure peripheral increasing mode */
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if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
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DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
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}else{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
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}
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/* configure memory increasing mode */
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if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
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DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
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}else{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
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}
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/* configure the direction of data transfer */
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if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
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}else{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
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}
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}
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/*!
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\brief enable DMA circulation mode
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_circulation_enable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN;
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}
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/*!
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\brief disable DMA circulation mode
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_circulation_disable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN;
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}
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/*!
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\brief enable memory to memory mode
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_memory_to_memory_enable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M;
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}
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/*!
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\brief disable memory to memory mode
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_memory_to_memory_disable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M;
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}
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/*!
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\brief enable DMA channel
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_channel_enable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN;
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}
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/*!
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\brief disable DMA channel
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval none
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*/
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void dma_channel_disable(dma_channel_enum channelx)
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{
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DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
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}
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/*!
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\brief set DMA peripheral base address
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\param[in] channelx: specify which DMA channel to set peripheral base address
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] address: peripheral base address
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\param[out] none
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\retval none
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*/
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void dma_periph_address_config(dma_channel_enum channelx, uint32_t address)
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{
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DMA_CHPADDR(channelx) = address;
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}
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/*!
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\brief set DMA memory base address
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\param[in] channelx: specify which DMA channel to set memory base address
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] address: memory base address
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\param[out] none
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\retval none
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*/
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void dma_memory_address_config(dma_channel_enum channelx, uint32_t address)
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{
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DMA_CHMADDR(channelx) = address;
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}
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/*!
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\brief set the number of remaining data to be transferred by the DMA
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\param[in] channelx: specify which DMA channel to set number
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] number: the number of remaining data to be transferred by the DMA
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\param[out] none
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\retval none
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*/
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void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number)
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{
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DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK);
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}
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/*!
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\brief get the number of remaining data to be transferred by the DMA
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\param[in] channelx: specify which DMA channel to set number
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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\retval the number of remaining data to be transferred by the DMA
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*/
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uint32_t dma_transfer_number_get(dma_channel_enum channelx)
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{
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return (uint32_t)DMA_CHCNT(channelx);
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}
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/*!
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\brief configure priority level of DMA channel
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] priority: priority level of this channel
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only one parameter can be selected which is shown as below:
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\arg DMA_PRIORITY_LOW: low priority
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\arg DMA_PRIORITY_MEDIUM: medium priority
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\arg DMA_PRIORITY_HIGH: high priority
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\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
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\param[out] none
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\retval none
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*/
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void dma_priority_config(dma_channel_enum channelx, uint32_t priority)
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{
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uint32_t ctl;
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_PRIO;
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ctl |= priority;
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DMA_CHCTL(channelx) = ctl;
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}
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/*!
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\brief configure transfer data width of memory
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] mwidth: transfer data width of memory
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only one parameter can be selected which is shown as below:
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\arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
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\arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
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\arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
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\param[out] none
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\retval none
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*/
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void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth)
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{
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uint32_t ctl;
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_MWIDTH;
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ctl |= mwidth;
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DMA_CHCTL(channelx) = ctl;
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}
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/*!
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\brief configure transfer data width of peripheral
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[in] pwidth: transfer data width of peripheral
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only one parameter can be selected which is shown as below:
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\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
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\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
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\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
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\param[out] none
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\retval none
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*/
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void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth)
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{
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uint32_t ctl;
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/* acquire DMA_CHxCTL register */
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ctl = DMA_CHCTL(channelx);
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/* assign regiser */
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ctl &= ~DMA_CHXCTL_PWIDTH;
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ctl |= pwidth;
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DMA_CHCTL(channelx) = ctl;
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}
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/*!
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\brief enable next address increasement algorithm of memory
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\param[in] channelx: specify which DMA channel to set
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only one parameter can be selected which is shown as below:
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\arg DMA_CHx(x=0..4)
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\param[out] none
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|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_memory_increase_enable(dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable next address increasement algorithm of memory
|
||
|
|
\param[in] channelx: specify which DMA channel to set
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_memory_increase_disable(dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable next address increasement algorithm of peripheral
|
||
|
|
\param[in] channelx: specify which DMA channel to set
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_periph_increase_enable(dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable next address increasement algorithm of peripheral
|
||
|
|
\param[in] channelx: specify which DMA channel to set
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_periph_increase_disable(dma_channel_enum channelx)
|
||
|
|
{
|
||
|
|
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief configure the direction of data transfer on the channel
|
||
|
|
\param[in] channelx: specify which DMA channel to set
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] direction: specify the direction of data transfer
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
|
||
|
|
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction)
|
||
|
|
{
|
||
|
|
if(DMA_PERIPHERAL_TO_MEMORY == direction){
|
||
|
|
DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR;
|
||
|
|
} else {
|
||
|
|
DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check DMA flag is set or not
|
||
|
|
\param[in] channelx: specify which DMA channel to get flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_FLAG_G: global interrupt flag of channel
|
||
|
|
\arg DMA_FLAG_FTF: full transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_HTF: half transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_ERR: error flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval FlagStatus: SET or RESET
|
||
|
|
*/
|
||
|
|
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
FlagStatus reval;
|
||
|
|
|
||
|
|
if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){
|
||
|
|
reval = SET;
|
||
|
|
}else{
|
||
|
|
reval = RESET;
|
||
|
|
}
|
||
|
|
|
||
|
|
return reval;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief clear DMA a channel flag
|
||
|
|
\param[in] channelx: specify which DMA channel to clear flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_FLAG_G: global interrupt flag of channel
|
||
|
|
\arg DMA_FLAG_FTF: full transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_HTF: half transfer finish flag of channel
|
||
|
|
\arg DMA_FLAG_ERR: error flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
DMA_INTC |= DMA_FLAG_ADD(flag, channelx);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief check DMA flag and interrupt enable bit is set or not
|
||
|
|
\param[in] channelx: specify which DMA channel to get flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_INT_FLAG_FTF: transfer finish flag of channel
|
||
|
|
\arg DMA_INT_FLAG_HTF: half transfer finish flag of channel
|
||
|
|
\arg DMA_INT_FLAG_ERR: error flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval FlagStatus: SET or RESET
|
||
|
|
*/
|
||
|
|
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
|
||
|
|
|
||
|
|
switch(flag){
|
||
|
|
case DMA_INT_FLAG_FTF:
|
||
|
|
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
|
||
|
|
interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE;
|
||
|
|
break;
|
||
|
|
case DMA_INT_FLAG_HTF:
|
||
|
|
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
|
||
|
|
interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE;
|
||
|
|
break;
|
||
|
|
case DMA_INT_FLAG_ERR:
|
||
|
|
interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx);
|
||
|
|
interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if(interrupt_flag && interrupt_enable){
|
||
|
|
return SET;
|
||
|
|
}else{
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief clear DMA a channel interrupt flag
|
||
|
|
\param[in] channelx: specify which DMA channel to clear flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] flag: specify get which flag
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_INT_FLAG_G: global interrupt flag of channel
|
||
|
|
\arg DMA_INT_FLAG_FTF: transfer finish flag of channel
|
||
|
|
\arg DMA_INT_FLAG_HTF: half transfer finish flag of channel
|
||
|
|
\arg DMA_INT_FLAG_ERR: error flag of channel
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag)
|
||
|
|
{
|
||
|
|
DMA_INTC |= DMA_FLAG_ADD(flag,channelx);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief enable DMA interrupt
|
||
|
|
\param[in] channelx: specify which DMA channel to set
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] source: specify which interrupt to enable
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_INT_ERR: channel error interrupt
|
||
|
|
\arg DMA_INT_HTF: channel half transfer finish interrupt
|
||
|
|
\arg DMA_INT_FTF: channel full transfer finish interrupt
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source)
|
||
|
|
{
|
||
|
|
DMA_CHCTL(channelx) |= source;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief disable DMA interrupt
|
||
|
|
\param[in] channelx: specify which DMA channel to set
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_CHx(x=0..4)
|
||
|
|
\param[in] source: specify which interrupt to disable
|
||
|
|
only one parameter can be selected which is shown as below:
|
||
|
|
\arg DMA_INT_ERR: channel error interrupt
|
||
|
|
\arg DMA_INT_HTF: channel half transfer finish interrupt
|
||
|
|
\arg DMA_INT_FTF: channel full transfer finish interrupt
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source)
|
||
|
|
{
|
||
|
|
DMA_CHCTL(channelx) &= ~source;
|
||
|
|
}
|