623 lines
20 KiB
C
623 lines
20 KiB
C
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//*****************************************************************************
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//
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// watchdog.c - Driver for the Watchdog Timer Module.
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//
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// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup watchdog_api
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//! @{
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//
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//*****************************************************************************
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#include <stdbool.h>
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#include <stdint.h>
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_types.h"
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#include "inc/hw_watchdog.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/watchdog.h"
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//*****************************************************************************
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//
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//! Determines if the watchdog timer is enabled.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function checks to see if the watchdog timer is enabled.
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//!
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//! \return Returns \b true if the watchdog timer is enabled and \b false
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//! if it is not.
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//
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//*****************************************************************************
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bool
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WatchdogRunning(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// See if the watchdog timer module is enabled, and return.
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//
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return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN);
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function enables the watchdog timer counter and interrupt.
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//!
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//! \note This function has no effect if the watchdog timer has been locked.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogEnable(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Enable the watchdog timer module.
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//
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HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer reset.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function enables the capability of the watchdog timer to issue a reset
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//! to the processor after a second timeout condition.
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//!
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//! \note This function has no effect if the watchdog timer has been locked.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogResetEnable(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Enable the watchdog reset.
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//
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HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN;
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}
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//*****************************************************************************
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//
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//! Disables the watchdog timer reset.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function disables the capability of the watchdog timer to issue a
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//! reset to the processor after a second timeout condition.
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//!
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//! \note This function has no effect if the watchdog timer has been locked.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogResetDisable(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Disable the watchdog reset.
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//
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HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer lock mechanism.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function locks out write access to the watchdog timer registers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogLock(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
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// register causes the lock to go into effect.
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//
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HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED;
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}
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//*****************************************************************************
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//
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//! Disables the watchdog timer lock mechanism.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function enables write access to the watchdog timer registers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogUnlock(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Unlock watchdog register writes.
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//
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HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
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}
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//*****************************************************************************
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//
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//! Gets the state of the watchdog timer lock mechanism.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function returns the lock state of the watchdog timer registers.
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//!
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//! \return Returns \b true if the watchdog timer registers are locked, and
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//! \b false if they are not locked.
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//
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//*****************************************************************************
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bool
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WatchdogLockState(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Get the lock state.
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//
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return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
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}
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//*****************************************************************************
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//
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//! Sets the watchdog timer reload value.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//! \param ui32LoadVal is the load value for the watchdog timer.
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//!
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//! This function configures the value to load into the watchdog timer when the
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//! count reaches zero for the first time; if the watchdog timer is running
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//! when this function is called, then the value is immediately loaded into the
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//! watchdog timer counter. If the \e ui32LoadVal parameter is 0, then an
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//! interrupt is immediately generated.
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//!
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//! \note This function has no effect if the watchdog timer has been locked.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Set the load register.
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//
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HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal;
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}
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//*****************************************************************************
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//
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//! Gets the watchdog timer reload value.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function gets the value that is loaded into the watchdog timer when
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//! the count reaches zero for the first time.
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//!
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//! \return None.
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//
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//*****************************************************************************
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uint32_t
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WatchdogReloadGet(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Get the load register.
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//
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return(HWREG(ui32Base + WDT_O_LOAD));
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}
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//*****************************************************************************
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//
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//! Gets the current watchdog timer value.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//!
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//! This function reads the current value of the watchdog timer.
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//!
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//! \return Returns the current value of the watchdog timer.
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//
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//*****************************************************************************
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uint32_t
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WatchdogValueGet(uint32_t ui32Base)
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{
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//
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// Check the arguments.
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//
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ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
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//
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// Get the current watchdog timer register value.
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//
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return(HWREG(ui32Base + WDT_O_VALUE));
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}
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//*****************************************************************************
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//
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//! Registers an interrupt handler for the watchdog timer interrupt.
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//!
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//! \param ui32Base is the base address of the watchdog timer module.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! watchdog timer interrupt occurs.
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//!
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//! This function does the actual registering of the interrupt handler. This
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//! function also enables the global interrupt in the interrupt controller; the
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//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the
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//! interrupt handler's responsibility to clear the interrupt source via
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//! WatchdogIntClear().
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//!
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||
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//! \sa IntRegister() for important information about registering interrupt
|
||
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//! handlers.
|
||
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//!
|
||
|
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//! \note For parts with a watchdog timer module that has the ability to
|
||
|
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//! generate an NMI instead of a standard interrupt, this function registers
|
||
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//! the standard watchdog interrupt handler. To register the NMI watchdog
|
||
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|
//! handler, use IntRegister() to register the handler for the
|
||
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//! \b FAULT_NMI interrupt.
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||
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//!
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||
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//! \return None.
|
||
|
|
//
|
||
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//*****************************************************************************
|
||
|
|
void
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||
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WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
|
||
|
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{
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||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
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//
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||
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// Register the interrupt handler.
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||
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//
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||
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IntRegister(INT_WATCHDOG_TM4C123, pfnHandler);
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||
|
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|
||
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//
|
||
|
|
// Enable the watchdog timer interrupt.
|
||
|
|
//
|
||
|
|
IntEnable(INT_WATCHDOG_TM4C123);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Unregisters an interrupt handler for the watchdog timer interrupt.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//!
|
||
|
|
//! This function does the actual unregistering of the interrupt handler. This
|
||
|
|
//! function clears the handler to be called when a watchdog timer interrupt
|
||
|
|
//! occurs. This function also masks off the interrupt in the interrupt
|
||
|
|
//! controller so that the interrupt handler no longer is called.
|
||
|
|
//!
|
||
|
|
//! \sa IntRegister() for important information about registering interrupt
|
||
|
|
//! handlers.
|
||
|
|
//!
|
||
|
|
//! \note For parts with a watchdog timer module that has the ability to
|
||
|
|
//! generate an NMI instead of a standard interrupt, this function unregisters
|
||
|
|
//! the standard watchdog interrupt handler. To unregister the NMI watchdog
|
||
|
|
//! handler, use IntUnregister() to unregister the handler for the
|
||
|
|
//! \b FAULT_NMI interrupt.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
WatchdogIntUnregister(uint32_t ui32Base)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Disable the interrupt.
|
||
|
|
//
|
||
|
|
IntDisable(INT_WATCHDOG_TM4C123);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Unregister the interrupt handler.
|
||
|
|
//
|
||
|
|
IntUnregister(INT_WATCHDOG_TM4C123);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Enables the watchdog timer interrupt.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//!
|
||
|
|
//! This function enables the watchdog timer interrupt.
|
||
|
|
//!
|
||
|
|
//! \note This function has no effect if the watchdog timer has been locked.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
WatchdogIntEnable(uint32_t ui32Base)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Enable the watchdog interrupt.
|
||
|
|
//
|
||
|
|
HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Gets the current watchdog timer interrupt status.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//! \param bMasked is \b false if the raw interrupt status is required and
|
||
|
|
//! \b true if the masked interrupt status is required.
|
||
|
|
//!
|
||
|
|
//! This function returns the interrupt status for the watchdog timer module.
|
||
|
|
//! Either the raw interrupt status or the status of interrupt that is allowed
|
||
|
|
//! to reflect to the processor can be returned.
|
||
|
|
//!
|
||
|
|
//! \return Returns the current interrupt status, where a 1 indicates that the
|
||
|
|
//! watchdog interrupt is active, and a 0 indicates that it is not active.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
uint32_t
|
||
|
|
WatchdogIntStatus(uint32_t ui32Base, bool bMasked)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Return either the interrupt status or the raw interrupt status as
|
||
|
|
// requested.
|
||
|
|
//
|
||
|
|
if(bMasked)
|
||
|
|
{
|
||
|
|
return(HWREG(ui32Base + WDT_O_MIS));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return(HWREG(ui32Base + WDT_O_RIS));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Clears the watchdog timer interrupt.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//!
|
||
|
|
//! The watchdog timer interrupt source is cleared, so that it no longer
|
||
|
|
//! asserts.
|
||
|
|
//!
|
||
|
|
//! \note Because there is a write buffer in the Cortex-M processor, it may
|
||
|
|
//! take several clock cycles before the interrupt source is actually cleared.
|
||
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
||
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
||
|
|
//! returning from the interrupt handler before the interrupt source is
|
||
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
||
|
|
//! being immediately reentered (because the interrupt controller still sees
|
||
|
|
//! the interrupt source asserted). This function has no effect if the watchdog
|
||
|
|
//! timer has been locked.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
WatchdogIntClear(uint32_t ui32Base)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Clear the interrupt source.
|
||
|
|
//
|
||
|
|
HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Sets the type of interrupt generated by the watchdog.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//! \param ui32Type is the type of interrupt to generate.
|
||
|
|
//!
|
||
|
|
//! This function sets the type of interrupt that is generated if the watchdog
|
||
|
|
//! timer expires. \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to
|
||
|
|
//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to
|
||
|
|
//! generate a non-maskable interrupt (NMI).
|
||
|
|
//!
|
||
|
|
//! When configured to generate an NMI, the watchdog interrupt must still be
|
||
|
|
//! enabled with WatchdogIntEnable(), and it must still be cleared inside the
|
||
|
|
//! NMI handler with WatchdogIntClear().
|
||
|
|
//!
|
||
|
|
//! \note The ability to select an NMI interrupt varies with the Tiva part
|
||
|
|
//! in use. Please consult the datasheet for the part you are using to
|
||
|
|
//! determine whether this support is available. This function has no effect if
|
||
|
|
//! the watchdog timer has been locked.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) ||
|
||
|
|
(ui32Type == WATCHDOG_INT_TYPE_NMI));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set the interrupt type.
|
||
|
|
//
|
||
|
|
HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) &
|
||
|
|
~WDT_CTL_INTTYPE) | ui32Type;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Enables stalling of the watchdog timer during debug events.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//!
|
||
|
|
//! This function allows the watchdog timer to stop counting when the processor
|
||
|
|
//! is stopped by the debugger. By doing so, the watchdog is prevented from
|
||
|
|
//! expiring (typically almost immediately from a human time perspective) and
|
||
|
|
//! resetting the system (if reset is enabled). The watchdog instead expires
|
||
|
|
//! after the appropriate number of processor cycles have been executed while
|
||
|
|
//! debugging (or at the appropriate time after the processor has been
|
||
|
|
//! restarted).
|
||
|
|
//!
|
||
|
|
//! \note This function has no effect if the watchdog timer has been locked.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
WatchdogStallEnable(uint32_t ui32Base)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Enable timer stalling.
|
||
|
|
//
|
||
|
|
HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Disables stalling of the watchdog timer during debug events.
|
||
|
|
//!
|
||
|
|
//! \param ui32Base is the base address of the watchdog timer module.
|
||
|
|
//!
|
||
|
|
//! This function disables the debug mode stall of the watchdog timer. By
|
||
|
|
//! doing so, the watchdog timer continues to count regardless of the processor
|
||
|
|
//! debug state.
|
||
|
|
//!
|
||
|
|
//! \note This function has no effect if the watchdog timer has been locked.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
WatchdogStallDisable(uint32_t ui32Base)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Disable timer stalling.
|
||
|
|
//
|
||
|
|
HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Close the Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|