375 lines
13 KiB
C
375 lines
13 KiB
C
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/*
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** ###################################################################
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** Processors: LPC54114J256BD64_cm4
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** LPC54114J256UK49_cm4
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**
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** Compilers: Keil ARM C/C++ Compiler
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** MCUXpresso Compiler
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**
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** Reference manual: LPC5411x User manual Rev. 1.1 25 May 2016
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** Version: rev. 1.0, 2016-04-29
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** Build: b161227
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** The Clear BSD License
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** Copyright (c) 2016 Freescale Semiconductor, Inc.
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** Copyright 2016 - 2017 NXP
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted (subject to the limitations in the disclaimer below) provided
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** that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2016-04-29)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file LPC54114_cm4
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* @version 1.0
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* @date 2016-04-29
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* @brief Device specific configuration file for LPC54114_cm4 (implementation
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* file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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#define NVALMAX (0x100)
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#define PVALMAX (0x20)
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#define MVALMAX (0x8000)
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#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */
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#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */
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#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
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#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
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#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
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#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
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extern void *__Vectors;
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
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48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
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static uint32_t GetWdtOscFreq(void)
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{
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uint8_t freq_sel, div_sel;
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div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1;
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freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
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return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
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}
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/* Find decoded N value for raw NDEC value */
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static uint32_t pllDecodeN(uint32_t NDEC)
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{
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uint32_t n, x, i;
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/* Find NDec */
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switch (NDEC)
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{
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case 0xFFF:
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n = 0;
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break;
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case 0x302:
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n = 1;
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break;
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case 0x202:
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n = 2;
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break;
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default:
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x = 0x080;
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n = 0xFFFFFFFF;
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for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--)
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{
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x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
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if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
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{
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/* Decoded value of NDEC */
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n = i;
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}
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}
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break;
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}
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return n;
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}
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/* Find decoded P value for raw PDEC value */
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static uint32_t pllDecodeP(uint32_t PDEC)
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{
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uint32_t p, x, i;
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/* Find PDec */
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switch (PDEC)
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{
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case 0xFF:
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p = 0;
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break;
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case 0x62:
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p = 1;
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break;
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case 0x42:
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p = 2;
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break;
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default:
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x = 0x10;
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p = 0xFFFFFFFF;
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for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--)
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{
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x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
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if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
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{
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/* Decoded value of PDEC */
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p = i;
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}
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}
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break;
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}
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return p;
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}
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/* Find decoded M value for raw MDEC value */
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static uint32_t pllDecodeM(uint32_t MDEC)
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{
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uint32_t m, i, x;
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/* Find MDec */
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switch (MDEC)
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{
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case 0xFFFFF:
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m = 0;
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break;
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case 0x18003:
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m = 1;
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break;
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case 0x10003:
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m = 2;
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break;
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default:
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x = 0x04000;
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m = 0xFFFFFFFF;
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for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--)
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{
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x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
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if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
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{
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/* Decoded value of MDEC */
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m = i;
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}
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}
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break;
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}
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return m;
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}
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/* Get predivider (N) from PLL NDEC setting */
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static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
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{
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uint32_t preDiv = 1;
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/* Direct input is not used? */
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if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
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{
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/* Decode NDEC value to get (N) pre divider */
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preDiv = pllDecodeN(nDecReg & 0x3FF);
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if (preDiv == 0)
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{
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preDiv = 1;
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}
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}
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/* Adjusted by 1, directi is used to bypass */
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return preDiv;
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}
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/* Get postdivider (P) from PLL PDEC setting */
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static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
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{
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uint32_t postDiv = 1;
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/* Direct input is not used? */
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if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
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{
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/* Decode PDEC value to get (P) post divider */
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postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
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if (postDiv == 0)
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{
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postDiv = 2;
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}
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}
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/* Adjusted by 1, directo is used to bypass */
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return postDiv;
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}
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/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
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static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
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{
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uint32_t mMult = 1;
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/* Decode MDEC value to get (M) multiplier */
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mMult = pllDecodeM(mDecReg & 0x1FFFF);
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/* Extra multiply by 2 needed? */
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if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0)
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{
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mMult = mMult << 1;
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}
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if (mMult == 0)
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{
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mMult = 1;
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}
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return mMult;
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}
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit(void)
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{
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) || (defined(__VFP_FP__) && !defined(__SOFTFP__))
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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SCB->VTOR = (uint32_t)&__Vectors;
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/* Optionally enable RAM banks that may be off by default at reset */
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#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
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SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
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#endif
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SystemInitHook();
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate(void)
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{
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uint32_t clkRate = 0;
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uint32_t prediv, postdiv;
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uint64_t workRate;
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switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
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{
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case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
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switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
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{
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case 0x00: /* FRO 12 MHz (fro_12m) */
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clkRate = CLK_FRO_12MHZ;
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break;
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case 0x01: /* CLKIN (clk_in) */
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clkRate = CLK_CLK_IN;
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break;
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case 0x02: /* Watchdog oscillator (wdt_clk) */
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clkRate = GetWdtOscFreq();
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break;
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default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
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if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
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{
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clkRate = CLK_FRO_96MHZ;
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}
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else
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{
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clkRate = CLK_FRO_48MHZ;
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}
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break;
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}
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break;
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case 0x02: /* System PLL clock (pll_clk)*/
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switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
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{
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case 0x00: /* FRO 12 MHz (fro_12m) */
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clkRate = CLK_FRO_12MHZ;
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break;
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case 0x01: /* CLKIN (clk_in) */
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clkRate = CLK_CLK_IN;
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break;
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case 0x02: /* Watchdog oscillator (wdt_clk) */
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clkRate = GetWdtOscFreq();
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break;
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case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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clkRate = CLK_RTC_32K_CLK;
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break;
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default:
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break;
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}
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if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
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{
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/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
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prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
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postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
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/* Adjust input clock */
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clkRate = clkRate / prediv;
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/* If using the SS, use the multiplier */
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if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK)
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{
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/* MDEC used for rate */
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workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0);
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}
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else
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{
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/* SS multipler used for rate */
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workRate = 0;
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/* Adjust by fractional */
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workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800);
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}
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clkRate = workRate / ((uint64_t)postdiv);
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}
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break;
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case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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clkRate = CLK_RTC_32K_CLK;
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break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ----------------------------------------------------------------------------
|
||
|
|
-- SystemInitHook()
|
||
|
|
---------------------------------------------------------------------------- */
|
||
|
|
|
||
|
|
__attribute__ ((weak)) void SystemInitHook (void) {
|
||
|
|
/* Void implementation of the weak function. */
|
||
|
|
}
|