417 lines
10 KiB
ArmAsm
417 lines
10 KiB
ArmAsm
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include <rtconfig.h>
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#include <armv6.h>
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#define CONFIG_STACKSIZE 512
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#define FPEXC_EN (1 << 30) /* VFP enable bit */
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.equ I_BIT, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_BIT, 0x40 @ when F bit is set, FIQ is disabled
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#.equ USERMODE, 0x10
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#.equ FIQMODE, 0x11
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#.equ IRQMODE, 0x12
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#.equ SVCMODE, 0x13
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#.equ ABORTMODE, 0x17
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#.equ UNDEFMODE, 0x1b
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#.equ MODEMASK, 0x1f
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#.equ NOINT, 0xc0
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.equ RAM_BASE, 0x00000000 /*Start address of RAM*/
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.equ ROM_BASE, 0xA0000000 /*Start address of Flash*/
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#define FH81_INTC_BASE 0xE0200000
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/*
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*************************************************************************
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*
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* Jump vector table
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*
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*************************************************************************
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*/
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.section .init, "ax"
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.code 32
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.globl _start
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_start:
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b reset
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ldr pc, _vector_undef
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ldr pc, _vector_swi
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ldr pc, _vector_pabt
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ldr pc, _vector_dabt
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ldr pc, _vector_resv
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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_vector_undef: .word vector_undef
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_vector_swi: .word vector_swi
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_vector_pabt: .word vector_pabt
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_vector_dabt: .word vector_dabt
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_vector_resv: .word vector_resv
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_vector_irq: .word vector_irq
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_vector_fiq: .word vector_fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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/*
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* rtthread kernel start and end
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* which are defined in linker script
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*/
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.globl _rtthread_start
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_rtthread_start:
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.word _start
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.globl _rtthread_end
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_rtthread_end:
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.word _end
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/*
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* rtthread bss start and end which are defined in linker script
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word __bss_end
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word _irq_stack_start + 1024
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word _fiq_stack_start + 1024
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.globl UNDEFINED_STACK_START
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UNDEFINED_STACK_START:
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.word _undefined_stack_start + CONFIG_STACKSIZE
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.globl ABORT_STACK_START
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ABORT_STACK_START:
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.word _abort_stack_start + CONFIG_STACKSIZE
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.globl _STACK_START
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_STACK_START:
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.word _svc_stack_start + 4096
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/* ----------------------------------entry------------------------------*/
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reset:
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/* set the cpu to SVC32 mode */
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mrs r0,cpsr
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bic r0,r0,#MODEMASK
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orr r0,r0,#SVCMODE
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msr cpsr,r0
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@vector 0x0
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@enable icaches
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@little endian
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@disable dcaches, mmu
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//ldr r0, =0x00400078
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@ldr r0, =0x0000107a
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// mcr p15, 0, r0, c1, c0, 0
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//read
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ldr r0, =0x0
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mrc p15, 0, r0, c1, c0, 0
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//change
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ldr r0, =0x00400078
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mcr p15, 0, r0, c1, c0, 0
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//check
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ldr r0, =0x0
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mrc p15, 0, r0, c1, c0, 0
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ldr r0, =0x00000000
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mcr p15, 0, r0, c8, c7, 0 @ Flush TLB
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mcr p15, 0, r0, c7, c7, 0 @ Flush Caches
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mcr p15, 0, r0, c7, c10, 4 @ Flush Write Buffer
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/* mask all IRQs by clearing all bits in the INTMRs set low and high to 0 */
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ldr r1, =FH81_INTC_BASE
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ldr r0, =0x0
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str r0, [r1]
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str r0, [r1, #4]
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/* setup stack */
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bl stack_setup
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* enable_unaligned_access */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x02 /*Clear the A bit, bit 1*/
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and r0, r0, #(1 << 22) /*Set the U bit, bit 22*/
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mcr p15, 0, r0, c1, c0, 0
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#ifdef RT_USING_VFP
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bl vfp_init
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#endif
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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.global cpu_reset
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cpu_reset:
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#ldr r0, =0xfffffd00
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#ldr r1, =(AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST)
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#str r1, [r0]
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#mov pc, lr
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B cpu_reset
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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.macro push_exp_reg
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sub sp, sp, #S_FRAME_SIZE @/* Sizeof(struct rt_hw_stack) */
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stmib sp, {r0 - r12} @/* Calling r0-r12 */
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mov r0, sp
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mrs r6, spsr @/* Save CPSR */
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str lr, [r0, #S_PC] @/* Push PC */
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str r6, [r0, #S_CPSR] @/* Push CPSR */
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@ switch to SVC mode with no interrupt
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msr cpsr_c, #I_BIT|F_BIT|SVCMODE
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str sp, [r0, #S_SP] @/* Save calling SP */
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str lr, [r0, #S_LR] @/* Save calling PC */
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.endm
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#ifdef RT_USING_VFP
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__ret_to_undef:
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ldmfd sp!, {r4} @ pop task's cpsr to spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12}
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add sp, sp, #4
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ldmfd sp!, {lr,pc}^
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#endif
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/* exception handlers */
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.align 5
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vector_undef:
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push_exp_reg
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#ifdef RT_USING_VFP
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cps #UNDEFMODE
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ldr r2, [r0, #S_PC] @ r2=faulted PC+4
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adr r9, __ret_to_undef @ r9=exception success return
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sub r1, r2, #4
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ldr r0, [r1] @ r0=faulted instruction
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bl undef_entry
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mov r0, sp
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#endif
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bl rt_hw_trap_udef
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.align 5
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vector_swi:
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push_exp_reg
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bl rt_hw_trap_swi
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.align 5
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vector_pabt:
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push_exp_reg
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bl rt_hw_trap_pabt
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.align 5
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vector_dabt:
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push_exp_reg
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bl rt_hw_trap_dabt
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.align 5
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vector_resv:
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push_exp_reg
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bl rt_hw_trap_resv
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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@
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#ifdef RT_USING_VFP
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vmrs r0, fpexc
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stmfd sp!, {r0} @ save VFP status -- irq_fpexc = fpexc
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bic r0, r0, #FPEXC_EN @ always disable VFP so we can
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@ lazily save/restore the old state.
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vmsr fpexc, r0
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#endif
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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#ifdef RT_USING_VFP
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ldmfd sp!, {r1}
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vmrs r0, fpexc
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tst r0, #FPEXC_EN @ irq used VFP?
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bicne r1, r0, #FPEXC_EN @ if irq used VFP, then clear fpexc.en bit
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vmsr fpexc, r1 @ restore VFP status
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@ if irq not used VFP, then fpexc = irq_fpexc
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@ if irq used VFP, then disable VFP
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#endif
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@ if rt_thread_switch_interrupt_flag set, jump to
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@ rt_hw_context_switch_interrupt_do and don't return
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do
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ldmfd sp!, {r0-r12,lr}
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@mrs r8,spsr
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@msr cpsr, r8
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subs pc, lr, #4
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.align 5
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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rt_hw_context_switch_interrupt_do:
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mov r1, #0 @ clear flag
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str r1, [r0]
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ldmfd sp!, {r0-r12,lr}@ reload saved registers
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stmfd sp, {r0-r2} @ save r0-r2
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mrs r0, spsr @ get cpsr of interrupt thread
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sub r1, sp, #4*3
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sub r2, lr, #4 @ save old task's pc to r2
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@ switch to SVC mode with no interrupt
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msr cpsr_c, #I_BIT|F_BIT|SVCMODE
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stmfd sp!, {r2} @ push old task's pc
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stmfd sp!, {r3-r12,lr}@ push old task's lr,r12-r4
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ldmfd r1, {r1-r3} @ restore r0-r2 of the interrupt thread
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stmfd sp!, {r1-r3} @ push old task's r0-r2
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stmfd sp!, {r0} @ push old task's cpsr
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] @ store sp in preempted tasks's TCB
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] @ get new task's stack pointer
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ldmfd sp!, {r4} @ pop new task's cpsr to spsr
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msr spsr_cxsf, r4
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#ifdef RT_USING_VFP
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vmrs r0, fpexc
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bic r0, r0, #FPEXC_EN @ always disable VFP so we can
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||
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@ lazily save/restore the old state.
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||
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vmsr fpexc, r0
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||
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#endif
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||
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||
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ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
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||
|
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||
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||
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stack_setup:
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||
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|
mrs r0, cpsr
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||
|
|
bic r0, r0, #MODEMASK
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||
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|
orr r1, r0, #UNDEFMODE|NOINT
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||
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|
msr cpsr_cxsf, r1 /* undef mode */
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||
|
|
ldr sp, UNDEFINED_STACK_START
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||
|
|
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||
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|
orr r1,r0,#ABORTMODE|NOINT
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||
|
|
msr cpsr_cxsf,r1 /* abort mode */
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||
|
|
ldr sp, ABORT_STACK_START
|
||
|
|
|
||
|
|
orr r1,r0,#IRQMODE|NOINT
|
||
|
|
msr cpsr_cxsf,r1 /* IRQ mode */
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||
|
|
ldr sp, IRQ_STACK_START
|
||
|
|
|
||
|
|
orr r1,r0,#FIQMODE|NOINT
|
||
|
|
msr cpsr_cxsf,r1 /* FIQ mode */
|
||
|
|
ldr sp, FIQ_STACK_START
|
||
|
|
|
||
|
|
bic r0,r0,#MODEMASK
|
||
|
|
orr r1,r0,#SVCMODE|NOINT
|
||
|
|
msr cpsr_cxsf,r1 /* SVC mode */
|
||
|
|
|
||
|
|
ldr sp, _STACK_START
|
||
|
|
|
||
|
|
/* USER mode is not initialized. */
|
||
|
|
bx lr /* The LR register may be not valid for the mode changes.*/
|
||
|
|
|
||
|
|
/*/*}*/
|