2020-12-21 14:34:01 +08:00
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/**************************************************************************//**
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* @file pwm.h
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* @version V1.00
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* $Revision: 3 $
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* $Date: 15/05/19 10:16a $
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* @brief NUC980 series PWM driver header file
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*
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* @note
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __NU_PWM_H__
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#define __NU_PWM_H__
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#include "nuc980.h"
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#include "nu_sys.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
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@{
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*/
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#define PWM_OFFSET 0xc ///< each channel has 3 control registers which occupies 12 bytes
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// Timer channel identity information
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#define PWM_TIMER_NUM 8 ///< Total PWM channel count
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#define PWM_TIMER_MIN 0 ///< Min PWM channel number
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#define PWM_TIMER_MAX 7 ///< Max PWM channel number
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#define PWM0_TIMER0 0 ///< PWM0 channel 0
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#define PWM0_TIMER1 1 ///< PWM0 channel 1
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#define PWM0_TIMER2 2 ///< PWM0 channel 2
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#define PWM0_TIMER3 3 ///< PWM0 channel 3
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#define PWM1_TIMER0 4 ///< PWM1 channel 0
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#define PWM1_TIMER1 5 ///< PWM1 channel 1
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#define PWM1_TIMER2 6 ///< PWM1 channel 2
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#define PWM1_TIMER3 7 ///< PWM1 channel 3
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//ioctl command
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2021-05-14 11:53:46 +08:00
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#define START_PWMTIMER 0 ///< Start PWM ioctl command
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2020-12-21 14:34:01 +08:00
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#define STOP_PWMTIMER 1 ///< Stop PWM ioctl command
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#define SET_CSR 2 ///< Set CSR ioctl command
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#define SET_CP 3 ///< Set CP ioctl command
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#define SET_DZI 4 ///< Set dead zone ioctl command
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#define SET_INVERTER 5 ///< Set inverter ioctl command
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#define SET_MODE 6 ///< Set OP mode ioctl command
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#define ENABLE_DZ_GENERATOR 7 ///< Enable dead zone ioctl command
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#define DISABLE_DZ_GENERATOR 8 ///< Disable dead zone ioctl command
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#define ENABLE_PWMGPIOOUTPUT 9 ///< Enable PWM output ioctl command
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#define PWM_STOP_METHOD1 1 ///< PWM stop method 1
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#define PWM_STOP_METHOD2 2 ///< PWM stop method 2
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//#define PWM_STOP_METHOD3 3 not recommended
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//Timer default value
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#define DEFAULT_CSR CSRD16 ///< Default CSR value
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#define DEFAULT_CP 255 ///< Default CP value
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#define DEFAULT_DZI 50 ///< Default DZI value
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#define DEFAULT_CNR 19531 ///< Default CNR value
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#define DEFAULT_CMR (19531/4) ///< Default CMR value
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#define DEFAULT_MODE PWM_TOGGLE ///< Default OP mode
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// for PWM_PPR
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#define DZI_MIN 0 ///< Min DZI value
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#define DZI_MAX 255 ///< Max DZI value
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#define CP_MIN 0 ///< Min CP value
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#define CP_MAX 255 ///< Max CP value
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// for PWM_CSR
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#define CSR_MIN 0 ///< Min CSR value
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#define CSR_MAX 4 ///< Mac SCR value
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#define CSRD2 0x0 ///< Div by 2
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#define CSRD4 0x1 ///< Div by 4
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#define CSRD8 0x2 ///< Div by 8
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#define CSRD16 0x3 ///< Div by 16
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#define CSRD1 0x4 ///< Div by 1
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// for PWM_PCR
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#define PWMDZG_ENABLE 1 ///< Enable PWM dead zone
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#define PWMDZG_DISABLE 0 ///< Disable PWM dead zone
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#define PWM_ENABLE 1 ///< Enable PWM channel
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#define PWM_DISABLE 0 ///< Disable PWM channel
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#define PWM_TOGGLE 1 ///< PWM toggle mode
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#define PWM_ONESHOT 0 ///< PWM one-shot mode
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#define PWM_INVON 1 ///< Enable PWM inverter
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#define PWM_INVOFF 0 ///< Disable PWM inverter
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// for PWM_CNR
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#define CNR_MIN 0 ///< Min CNR value
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#define CNR_MAX 65535 ///< Mac CNR value
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// for PWM_CMR
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#define CMR_MIN 0 ///< Min CMR value
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#define CMR_MAX 65535 ///< Max CMR value
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// for pin control
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#define PWM00_GPF5 0 ///< PWM00 output on GPF5
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#define PWM01_GPF6 1 ///< PWM01 output on GPF6
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#define PWM02_GPF7 2 ///< PWM02 output on GPF7
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#define PWM03_GPF8 3 ///< PWM03 output on GPF8
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#define PWM00_GPG0 4 ///< PWM00 output on GPG0
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#define PWM01_GPG1 5 ///< PWM01 output on GPG1
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#define PWM02_GPG2 6 ///< PWM02 output on GPG2
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#define PWM03_GPG3 7 ///< PWM03 output on GPG3
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#define PWM00_GPD12 8 ///< PWM00 output on GPD12
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#define PWM01_GPD13 9 ///< PWM01 output on GPD13
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#define PWM02_GPD14 10 ///< PWM02 output on GPD14
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#define PWM03_GPD15 11 ///< PWM03 output on GPD15
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#define PWM00_GPG10 12 ///< PWM00 output on GPG10
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#define PWM01_GPA15 13 ///< PWM01 output on GPA15
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#define PWM02_GPA14 14 ///< PWM02 output on GPA14
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#define PWM03_GPA13 15 ///< PWM03 output on GPA13
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#define PWM02_GPB13 16 ///< PWM02 output on GPB13
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#define PWM10_GPB12 17 ///< PWM10 output on GPB12
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#define PWM11_GPB11 18 ///< PWM11 output on GPB11
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#define PWM12_GPB10 19 ///< PWM12 output on GPB10
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#define PWM13_GPB9 20 ///< PWM13 output on GPB9
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#define PWM10_GPG6 21 ///< PWM10 output on GPG6
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#define PWM11_GPG7 22 ///< PWM11 output on GPG7
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#define PWM12_GPG8 23 ///< PWM12 output on GPG8
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#define PWM13_GPG9 24 ///< PWM13 output on GPG9
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#define PWM10_GPG11 25 ///< PWM10 output on GPG11
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#define PWM11_GPG12 26 ///< PWM11 output on GPG12
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#define PWM12_GPG13 27 ///< PWM12 output on GPG13
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#define PWM13_GPG14 28 ///< PWM13 output on GPG14
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#define PWM10_GPF9 29 ///< PWM10 output on GPF9
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#define PWM11_GPF10 30 ///< PWM11 output on GPF10
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#define PWM12_GPE10 31 ///< PWM12 output on GPE10
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#define PWM13_GPE12 32 ///< PWM13 output on GPE12
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#define PWM_ERR_ID 0xFFFF1300 ///< PWM library ID
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//PWM Error code
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#define pwmInvalidTimerChannel (PWM_ERR_ID|1) ///< Invalid channel number
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#define pwmInvalidStructLength (PWM_ERR_ID|2) ///< Invalid structure length
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#define pwmInvalidIoctlCommand (PWM_ERR_ID|3) ///< Invalid ioctl command
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#define pwmInvalidStopMethod (PWM_ERR_ID|4) ///< Invalid stop mode
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#define pwmInvalidCPValue (PWM_ERR_ID|5) ///< Invalid CP value
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#define pwmInvalidDZIValue (PWM_ERR_ID|6) ///< Invalid DZI value
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#define pwmInvalidCSRValue (PWM_ERR_ID|7) ///< Invalid CSR value
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#define pwmInvalidDZGStatus (PWM_ERR_ID|8) ///< Invalid DZ status
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#define pwmInvalidTimerStatus (PWM_ERR_ID|9) ///< Invalid timer status
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#define pwmInvalidInverterValue (PWM_ERR_ID|10) ///< Invalid inverter value
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#define pwmInvalidModeStatus (PWM_ERR_ID|11) ///< Invalid OP mode
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#define pwmInvalidCNRValue (PWM_ERR_ID|12) ///< Invalid CNR value
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#define pwmInvalidCMRValue (PWM_ERR_ID|13) ///< Invalid CMR value
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#define pwmTimerNotOpen (PWM_ERR_ID|14) ///< PWM channel not stop
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#define pwmTimerBusy (PWM_ERR_ID|15) ///< PWM channel is busy
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#define pwmInvalidPin (PWM_ERR_ID|16) ///< Invalid PWM output pin
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/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
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/// @cond HIDDEN_SYMBOLS
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/** @addtogroup PWM_EXPORTED_STRUCTS PWM Exported Structs
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@{
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*/
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typedef union
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{
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UINT value;
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struct
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{
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UINT cp0: 8, cp1: 8, dzi0: 8, dzi1: 8;
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} field;
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} typePPR;
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typedef union
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{
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UINT value;
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struct
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{
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UINT csr0: 3, _reserved3: 1,
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csr1: 3, _reserved7: 1,
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csr2: 3, _reserved11: 1,
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csr3: 3, _reserved15: 1,
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_reserved16_31: 16;
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} field;
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} typeCSR;
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typedef union
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{
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UINT value;
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struct
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{
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UINT ch0_en: 1, _reserved1: 1, ch0_inverter: 1, ch0_mode: 1,
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grpup0_dzen: 1, grpup1_dzen: 1,
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_reserved6_7: 2,
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ch1_en: 1, _reserved9: 1, ch1_inverter: 1, ch1_mode: 1,
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ch2_en: 1, _reserved13: 1, ch2_inverter: 1, ch2_mode: 1,
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ch3_en: 1, _reserved17: 1, ch3_inverter: 1, ch3_mode: 1,
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_reserved20_31: 12;
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} field;
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} typePCR;
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typedef union
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{
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UINT value;
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struct
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{
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UINT cnr: 16, _reserved16_31: 16;
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} field;
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} typeCNR;
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typedef union
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{
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UINT value;
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struct
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{
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UINT cmr: 16, _reserved16_31: 16;
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} field;
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} typeCMR;
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// for write operation
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typedef union
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{
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UINT value;
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struct
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{
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UINT cnr: 16, cmr: 16;
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} field;
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} typePWMVALUE;
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// for read operation
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typedef struct
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{
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UINT volatile PDR;
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BOOL volatile InterruptFlag;
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BOOL _reversed0;
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BOOL _reversed1;
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BOOL _reversed2;
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} typePWMSTATUS;
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/*@}*/ /* end of group PWM_EXPORTED_STRUCTS */
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/// @endcond /* HIDDEN_SYMBOLS */
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/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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// function definition
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INT pwmInit(const INT nTimerIdentity);
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INT pwmExit(void);
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INT pwmOpen(const INT nTimerIdentity);
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INT pwmClose(const INT nTimerIdentity);
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INT pwmRead(const INT nTimerIdentity, PUCHAR pucStatusValue, const UINT uLength);
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INT pwmWrite(const INT nTimerIdentity, PUCHAR pucCNRCMRValue, const UINT uLength);
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INT pwmIoctl(const INT nTimerIdentity, const UINT uCommand, const UINT uIndication, UINT uValue);
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/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group PWM_Driver */
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/*@}*/ /* end of group Standard_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__NU_PWM_H__
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/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
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