380 lines
21 KiB
C
380 lines
21 KiB
C
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/******************************************************************************
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* @file nu_bpwm.h
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* @version V1.00
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* $Revision: 9 $
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* $Date: 18/06/07 3:47p $
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* @brief M031 series BPWM driver header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __NU_BPWM_H__
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#define __NU_BPWM_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup BPWM_Driver BPWM Driver
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@{
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*/
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/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
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@{
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*/
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#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */
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#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask */
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#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask */
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#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask */
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#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask */
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#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask */
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#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Counter Type Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */
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#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */
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#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Aligned Type Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */
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#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Output Level Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */
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#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */
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#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */
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#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Synchronous Start Function Control Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
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#define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
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#define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
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#define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Trigger Source Select Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point */
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#define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point */
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#define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point */
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#define BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point */
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#define BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point */
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#define BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point */
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#define BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Capture Control Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition */
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#define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Duty Interrupt Type Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (BPWM_INTEN_CMPDIEN0_Msk) /*!< BPWM duty interrupt triggered if down count match comparator */
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#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (BPWM_INTEN_CMPUIEN0_Msk) /*!< BPWM duty interrupt triggered if up down match comparator */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Load Mode Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_LOAD_MODE_IMMEDIATE (BPWM_CTL0_IMMLDEN0_Msk) /*!< BPWM immediately load mode */
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#define BPWM_LOAD_MODE_CENTER (BPWM_CTL0_CTRLD0_Msk) /*!< BPWM center load mode */
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/*---------------------------------------------------------------------------------------------------------*/
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/* Clock Source Select Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK */
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#define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow */
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#define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow */
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#define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow */
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#define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow */
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/*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */
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/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
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@{
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*/
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/**
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* @brief Enable timer synchronous start counting function of specified channel(s)
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
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* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
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* - \ref BPWM_SSCTL_SSRC_PWM0
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* - \ref BPWM_SSCTL_SSRC_PWM1
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* - \ref BPWM_SSCTL_SSRC_BPWM0
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* - \ref BPWM_SSCTL_SSRC_BPWM1
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* @return None
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* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
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* @note All channels share channel 0's setting.
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* \hideinitializer
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*/
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#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
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/**
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* @brief Disable timer synchronous start counting function of specified channel(s)
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
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* @return None
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* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
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* @note All channels share channel 0's setting.
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* \hideinitializer
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*/
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#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
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/**
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* @brief This macro enable BPWM counter synchronous start counting function.
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* @param[in] bpwm The pointer of the specified BPWM module
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* @return None
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* @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
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* To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
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* \hideinitializer
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*/
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#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
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/**
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* @brief This macro enable output inverter of specified channel(s)
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
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/**
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* @brief This macro get captured rising data
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
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* @return None
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* \hideinitializer
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*/
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#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
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/**
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* @brief This macro get captured falling data
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
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* @return None
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* \hideinitializer
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*/
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#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
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/**
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* @brief This macro mask output logic to high or low
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32LevelMask Output logic to high or low
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* @return None
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* @details This macro is used to mask output logic to high or low of specified channel(s).
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* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
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* \hideinitializer
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*/
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#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
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{ \
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(bpwm)->MSKEN = (u32ChannelMask); \
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(bpwm)->MSK = (u32LevelMask); \
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}
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/**
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* @brief This macro set the prescaler of all channels
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
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* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
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* @return None
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* \hideinitializer
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*/
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#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
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/**
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* @brief This macro get the prescaler of the selected channel
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5. This parameter is not used.
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* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
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* @details This macro is used to get the prescaler of specified channel.
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* @note All channels share channel 0's setting.
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* The clock of BPWM counter is divided by (u32Prescaler + 1).
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* \hideinitializer
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*/
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#define BPWM_GET_PRESCALER(bpwm, u32ChannelNum) (bpwm)->CLKPSC
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/**
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* @brief This macro set the duty of the selected channel
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
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* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next BPWM period
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* \hideinitializer
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*/
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#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
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/**
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* @brief This macro get the duty of the selected channel
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
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* @return Return the duty of specified channel. Valid values are between 0~0xFFFF
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* @details This macro is used to get the duty of specified channel.
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* \hideinitializer
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*/
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#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
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/**
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* @brief This macro set the period of all channels
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
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* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next BPWM period
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* @note BPWM counter will stop if period length set to 0
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* \hideinitializer
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*/
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#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
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/**
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* @brief This macro get the period of all channels
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
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* @return Return the period of specified channel.
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* @details This macro is used to get the period of specified channel.
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* \hideinitializer
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*/
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#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
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/**
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* @brief This macro set the BPWM aligned type
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
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* @param[in] u32AlignedType BPWM aligned type, valid values are:
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* - \ref BPWM_UP_COUNTER
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* - \ref BPWM_DOWN_COUNTER
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* - \ref BPWM_UP_DOWN_COUNTER
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* @return None
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* @note All channels share channel 0's setting.
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* \hideinitializer
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*/
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#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
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/**
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* @brief Clear counter of channel 0
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
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* @return None
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* @details This macro is used to clear counter of channel 0
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* \hideinitializer
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*/
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#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
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/**
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* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
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* @param[in] bpwm The pointer of the specified BPWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32ZeroLevel output level at zero point, valid values are:
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* - \ref BPWM_OUTPUT_NOTHING
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* - \ref BPWM_OUTPUT_LOW
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* - \ref BPWM_OUTPUT_HIGH
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* - \ref BPWM_OUTPUT_TOGGLE
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* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
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* - \ref BPWM_OUTPUT_NOTHING
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* - \ref BPWM_OUTPUT_LOW
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* - \ref BPWM_OUTPUT_HIGH
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* - \ref BPWM_OUTPUT_TOGGLE
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* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
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* - \ref BPWM_OUTPUT_NOTHING
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* - \ref BPWM_OUTPUT_LOW
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* - \ref BPWM_OUTPUT_HIGH
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* - \ref BPWM_OUTPUT_TOGGLE
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* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
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* - \ref BPWM_OUTPUT_NOTHING
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* - \ref BPWM_OUTPUT_LOW
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* - \ref BPWM_OUTPUT_HIGH
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* - \ref BPWM_OUTPUT_TOGGLE
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* @return None
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* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
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* \hideinitializer
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*/
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#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
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do{ \
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uint32_t i; \
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for(i = 0UL; i < 6UL; i++) { \
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if((u32ChannelMask) & (1UL << i)) { \
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(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1UL))) | ((u32ZeroLevel) << (i << 1UL))); \
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(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))); \
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(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1UL))) | ((u32CmpUpLevel) << (i << 1UL))); \
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(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))); \
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} \
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} \
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}while(0)
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/*---------------------------------------------------------------------------------------------------------*/
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/* Define BPWM functions prototype */
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/*---------------------------------------------------------------------------------------------------------*/
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uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
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uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
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void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
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void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
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uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
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void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
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void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
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void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||
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void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
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|
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
||
|
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void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||
|
|
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||
|
|
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||
|
|
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
|
||
|
|
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||
|
|
|
||
|
|
|
||
|
|
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
|
||
|
|
|
||
|
|
/*@}*/ /* end of group BPWM_Driver */
|
||
|
|
|
||
|
|
/*@}*/ /* end of group Standard_Driver */
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __NU_BPWM_H__ */
|
||
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|
||
|
|
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
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