93 lines
3.2 KiB
C
93 lines
3.2 KiB
C
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen header file for usart driver
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*/
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#ifndef __CK_USART_H
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#define __CK_USART_H
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#include <stdio.h>
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#include "errno.h"
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define BAUDRATE_DEFAULT 19200
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#define UART_BUSY_TIMEOUT 1000000
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#define UART_RECEIVE_TIMEOUT 1000
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#define UART_TRANSMIT_TIMEOUT 1000
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#define UART_MAX_FIFO 0x10
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/* UART register bit definitions */
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#define USR_UART_BUSY 0x01
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#define USR_UART_TFE 0x04
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#define USR_UART_RFNE 0x08
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#define LSR_DATA_READY 0x01
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#define LSR_THR_EMPTY 0x20
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#define IER_RDA_INT_ENABLE 0x01
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#define IER_THRE_INT_ENABLE 0x02
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#define IIR_RECV_LINE_ENABLE 0x04
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#define IIR_NO_ISQ_PEND 0x01
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#define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */
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#define LCR_PARITY_ENABLE 0x08 /* parity enabled */
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#define LCR_PARITY_EVEN 0x10 /* Even parity enabled */
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#define LCR_PARITY_ODD 0xef /* Odd parity enabled */
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#define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */
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#define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */
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#define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */
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#define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */
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#define LCR_STOP_BIT1 0xfb /* 1 stop bit */
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#define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */
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#define DW_LSR_PFE 0x80
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#define DW_LSR_TEMT 0x40
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#define DW_LSR_THRE 0x40
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#define DW_LSR_BI 0x10
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#define DW_LSR_FE 0x08
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#define DW_LSR_PE 0x04
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#define DW_LSR_OE 0x02
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#define DW_LSR_DR 0x01
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#define DW_LSR_TRANS_EMPTY 0x20
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#define DW_IIR_THR_EMPTY 0x02 /* threshold empty */
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#define DW_IIR_RECV_DATA 0x04 /* received data available */
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#define DW_IIR_RECV_LINE 0x06 /* receiver line status */
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#define DW_IIR_CHAR_TIMEOUT 0x0c /* character timeout */
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typedef struct
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{
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union
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{
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__IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
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__OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
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__IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */
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};
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union
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{
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__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */
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__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */
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};
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__IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */
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__IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */
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uint32_t RESERVED0;
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__IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */
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__IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */
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uint32_t RESERVED1[24];
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__IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */
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} ck_usart_reg_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CK_USART_H */
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