589 lines
17 KiB
C
589 lines
17 KiB
C
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/**
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* \file
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*
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* \brief SAM GPIO Driver for SAMB11
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*
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* Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include <gpio.h>
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/**
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* \internal
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* Internal driver device instance struct.
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*/
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struct gpio_module _gpio_instances[3];
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static void (*aon_handle_ext_wakeup_isr)(void) = (void (*)(void))0x1bc51;
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/**
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* \brief Initializes a gpio pin/group configuration structure to defaults.
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*
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* Initializes a given gpio pin/group configuration structure to a set of
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* known default values. This function should be called on all new
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* instances of these configuration structures before being modified by the
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* user application.
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*
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* The default configuration is as follows:
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* \li Input mode with internal pullup enabled
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*
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* \param[out] config Configuration structure to initialize to default values.
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*/
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void gpio_get_config_defaults(struct gpio_config *const config)
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{
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/* Default configuration values */
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config->direction = GPIO_PIN_DIR_INPUT;
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config->input_pull = GPIO_PIN_PULL_UP;
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config->powersave = false;
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config->aon_wakeup = false;
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}
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/**
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* \brief Writes a gpio pin configuration to the hardware module.
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*
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* Writes out a given configuration of a gpio pin configuration to the hardware
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* module. If the configuration is NULL then it releases the gpio pin.
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*
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* \note If the pin direction is set as an output, the pull-up/pull-down input
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* configuration setting is ignored. Also certain gpio pin is used by
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* FW and not available for user application. Please \ref gpio_pin
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* for list of gpio_pin available.
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*
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* \param[in] gpio_pin Index of the GPIO pin to configure.
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* \param[in] config Configuration settings for the pin.
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*
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* \return Status of initialization.
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* \retval STATUS_OK gpio configured correctly
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* \retval STATUS_ERR_INVALID_ARG Invalid gpio number, Certain gpios
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* are used by FW and not allowed to change.
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* \retval STATUS_RESOURCE_NOT_AVAILABLE Requested gpio is already in use.
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*
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*/
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enum status_code gpio_pin_set_config(const uint8_t gpio_pin,
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const struct gpio_config *config)
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{
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enum status_code status = STATUS_OK;
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/* Following GPIO's should never be modified by user.
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* GPIO_0 & GPIO_1 are used for SWD.
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*/
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if ((gpio_pin == PIN_LP_GPIO_0) || \
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(gpio_pin == PIN_LP_GPIO_1))
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{
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status = STATUS_ERR_INVALID_ARG;
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} else {
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if (gpio_pin <= 7) {
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LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
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} else if (gpio_pin <= 15) {
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LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
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} else if (gpio_pin <= 23) {
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LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
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} else if (44 <= gpio_pin && gpio_pin < 48) {
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/* Set GPIO_MSx as digital mode */
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AON_GP_REGS0->MS_GPIO_MODE.vec.ANALOG_ENABLE_ &= ~(1 << (gpio_pin - PIN_GPIO_MS4));
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}
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if ((gpio_pin == PIN_AO_GPIO_0) || (gpio_pin == PIN_AO_GPIO_1) ||
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(gpio_pin == PIN_AO_GPIO_2)) {
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/* Active Low, Always On Pull Enable Control */
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if (config->input_pull == GPIO_PIN_PULL_UP) {
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AON_GP_REGS0->AON_PULL_ENABLE.reg &= ~(1 << (31 - gpio_pin));
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} else {
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AON_GP_REGS0->AON_PULL_ENABLE.reg |= 1 << (31 - gpio_pin);
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}
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if (config->aon_wakeup) {
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/* Enable AON_GPIO_x to be a wakeup MCU from sleep mode */
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AON_GP_REGS0->AON_PINMUX_SEL.reg |= 1 << (4 * (31 - gpio_pin));
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/* Enable AON_GPIO_x to wake up the BLE domain from sleep mode */
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AON_PWR_SEQ0->GPIO_WAKEUP_CTRL.bit.BLE_ENABLE = 1;
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}
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} else {
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if(config->direction == GPIO_PIN_DIR_INPUT) {
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if(gpio_pin < 16) {
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GPIO0->OUTENCLR.reg = (1 << gpio_pin);
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} else if (gpio_pin < 32){
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GPIO1->OUTENCLR.reg = (1 << (gpio_pin % 16));
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} else {
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GPIO2->OUTENCLR.reg = (1 << (gpio_pin % 16));
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}
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/* pull_enable. */
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if (gpio_pin < 32) {
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switch(config->input_pull) {
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case GPIO_PIN_PULL_NONE:
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LPMCU_MISC_REGS0->PULL_ENABLE.reg |= (1 << gpio_pin);
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break;
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case GPIO_PIN_PULL_UP:
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LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
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break;
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case GPIO_PIN_PULL_DOWN:
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/* Set R-Type */
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LPMCU_MISC_REGS0->RTYPE_PAD_0.reg |= (1 << gpio_pin);
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/* Set REN */
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LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
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break;
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default:
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status = STATUS_ERR_INVALID_ARG;
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break;
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}
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}
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} else if(config->direction == GPIO_PIN_DIR_OUTPUT) {
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if (gpio_pin < 16) {
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GPIO0->OUTENSET.reg = (1 << gpio_pin);
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} else if (gpio_pin < 32) {
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GPIO1->OUTENSET.reg = (1 << (gpio_pin % 16));
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} else {
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GPIO2->OUTENSET.reg = (1 << (gpio_pin % 16));
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}
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}
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}
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}
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return status;
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}
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/**
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* \brief Retrieves the state of a gpio pin that is configured as an input.
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*
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* Reads the current logic level of a gpio pin and returns the current
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* level as a boolean value.
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*
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* \param[in] gpio_pin Index of the GPIO pin to read.
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*
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* \return Status of the gpio pin's input buffer.
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*/
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bool gpio_pin_get_input_level(const uint8_t gpio_pin)
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{
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uint32_t regval = 0;
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if (gpio_pin < 16) {
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regval = GPIO0->DATA.reg;
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regval &= (1 << gpio_pin);
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} else if (gpio_pin < 32) {
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regval = GPIO1->DATA.reg;
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regval &= (1 << (gpio_pin % 16));
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} else {
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regval = GPIO2->DATA.reg;
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regval &= (1 << (gpio_pin % 16));
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}
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return regval;
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}
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/**
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* \brief Retrieves the state of a gpio pin that is configured as an output.
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*
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* Reads the current logical output level of a gpio pin and returns the current
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* level as a boolean value.
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*
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* \param[in] gpio_pin Index of the GPIO pin to read.
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*
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* \return Status of the gpio pin's output buffer.
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*/
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bool gpio_pin_get_output_level(const uint8_t gpio_pin)
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{
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uint32_t regval = 0;
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if (gpio_pin < 16) {
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regval = GPIO0->DATAOUT.reg;
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regval &= (1 << gpio_pin);
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} else if (gpio_pin < 32) {
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regval = GPIO1->DATAOUT.reg;
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regval &= (1 << (gpio_pin % 16));
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} else {
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regval = GPIO2->DATAOUT.reg;
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regval &= (1 << (gpio_pin % 16));
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}
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return regval;
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}
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/**
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* \brief Sets the state of a gpio pin that is configured as an output.
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*
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* Sets the current output level of a gpio pin to a given logic level.
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*
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* \param[in] gpio_pin Index of the GPIO pin to write to.
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* \param[in] level Logical level to set the given pin to.
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*/
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void gpio_pin_set_output_level(const uint8_t gpio_pin, const bool level)
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{
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if (gpio_pin < 16) {
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if(level) {
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GPIO0->DATAOUT.reg |= (1 << gpio_pin);
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} else {
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GPIO0->DATAOUT.reg &= ~(1 << gpio_pin);
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}
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} else if (gpio_pin < 32) {
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if(level) {
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GPIO1->DATAOUT.reg |= (1 << (gpio_pin % 16));
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} else {
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GPIO1->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
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}
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} else {
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if(level) {
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GPIO2->DATAOUT.reg |= (1 << (gpio_pin % 16));
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} else {
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GPIO2->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
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}
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}
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}
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/**
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* \brief Toggles the state of a gpio pin that is configured as an output.
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*
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* Toggles the current output level of a gpio pin.
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*
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* \param[in] gpio_pin Index of the GPIO pin to toggle.
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*/
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void gpio_pin_toggle_output_level(const uint8_t gpio_pin)
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{
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if (gpio_pin < 16) {
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GPIO0->DATAOUT.reg ^= (1 << gpio_pin);
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} else if (gpio_pin < 32) {
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GPIO1->DATAOUT.reg ^= (1 << (gpio_pin % 16));
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} else {
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GPIO2->DATAOUT.reg ^= (1 << (gpio_pin % 16));
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}
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}
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/**
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* \brief Writes a GPIO pin configuration to the hardware module.
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*
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* Writes out a given configuration of a GPIO pin configuration to the hardware
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* module.
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*
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* \param[in] gpio_pin Index of the GPIO pin to toggle.
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* \param[in] pinmux_sel PINMUX selection.
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*/
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void gpio_pinmux_cofiguration(const uint8_t gpio_pin, uint16_t pinmux_sel)
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{
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uint8_t megamux_sel = (pinmux_sel >> 8) & 0xFF;
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pinmux_sel &= 0xFF;
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if (gpio_pin <= 7) {
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LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
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LPMCU_MISC_REGS0->PINMUX_SEL_0.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
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if (pinmux_sel == 0x01) {
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if (gpio_pin <= 3) {
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
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} else if (gpio_pin <= 7) {
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
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}
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}
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} else if (gpio_pin <= 15) {
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LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
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LPMCU_MISC_REGS0->PINMUX_SEL_1.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
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if (pinmux_sel == 0x01) {
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if (gpio_pin <= 11) {
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
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} else if (gpio_pin <= 15) {
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
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}
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}
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} else if (gpio_pin <= 23) {
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LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
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LPMCU_MISC_REGS0->PINMUX_SEL_2.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
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if (pinmux_sel == 0x01) {
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if (gpio_pin <= 19) {
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
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} else if (gpio_pin <= 23) {
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LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
|
||
|
|
LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Registers a callback
|
||
|
|
*
|
||
|
|
* Registers a callback function which is implemented by the user.
|
||
|
|
*
|
||
|
|
* \note The callback must be enabled by \ref gpio_enable_callback,
|
||
|
|
* in order for the interrupt handler to call it when the conditions for
|
||
|
|
* the callback type are met.
|
||
|
|
*
|
||
|
|
* \param[in] gpio_pin GPIO pin number
|
||
|
|
* \param[in] callback_func Pointer to callback function
|
||
|
|
* \param[in] callback_type Callback type given by an enum
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void gpio_register_callback(uint8_t gpio_pin, gpio_callback_t callback_func,
|
||
|
|
enum gpio_callback callback_type)
|
||
|
|
{
|
||
|
|
/* Sanity check arguments */
|
||
|
|
Assert(callback_func);
|
||
|
|
Assert(gpio_pin < 48);
|
||
|
|
|
||
|
|
uint8_t gpio_port = 0;
|
||
|
|
|
||
|
|
if (gpio_pin < 16) {
|
||
|
|
gpio_port = 0;
|
||
|
|
} else if (gpio_pin < 32) {
|
||
|
|
gpio_port = 1;
|
||
|
|
} else {
|
||
|
|
gpio_port = 2;
|
||
|
|
}
|
||
|
|
switch (callback_type) {
|
||
|
|
case GPIO_CALLBACK_LOW:
|
||
|
|
_gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
|
||
|
|
_gpio_instances[gpio_port].hw->INTPOLCLR.reg = 1 << (gpio_pin % 16);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case GPIO_CALLBACK_HIGH:
|
||
|
|
_gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
|
||
|
|
_gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case GPIO_CALLBACK_RISING:
|
||
|
|
_gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
|
||
|
|
_gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case GPIO_CALLBACK_FALLING:
|
||
|
|
_gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
|
||
|
|
_gpio_instances[gpio_port].hw->INTPOLCLR.reg = (1 << (gpio_pin % 16));
|
||
|
|
break;
|
||
|
|
|
||
|
|
case GPIO_CALLBACK_N:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
/* Register callback function */
|
||
|
|
_gpio_instances[gpio_port].callback[gpio_pin % 16] = callback_func;
|
||
|
|
/* Set the bit corresponding to the gpio pin */
|
||
|
|
_gpio_instances[gpio_port].callback_reg_mask |= (1 << (gpio_pin % 16));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Unregisters a callback
|
||
|
|
*
|
||
|
|
* Unregisters a callback function which is implemented by the user.
|
||
|
|
*
|
||
|
|
*
|
||
|
|
* \param[in] gpio_pin GPIO pin number
|
||
|
|
* \param[in] callback_type Callback type given by an enum
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void gpio_unregister_callback(uint8_t gpio_pin,
|
||
|
|
enum gpio_callback callback_type)
|
||
|
|
{
|
||
|
|
/* Sanity check arguments */
|
||
|
|
Assert(callback_func);
|
||
|
|
Assert(gpio_pin < 48);
|
||
|
|
|
||
|
|
uint8_t gpio_port = 0;
|
||
|
|
|
||
|
|
if (gpio_pin < 16) {
|
||
|
|
gpio_port = 0;
|
||
|
|
} else if (gpio_pin < 32) {
|
||
|
|
gpio_port = 1;
|
||
|
|
} else {
|
||
|
|
gpio_port = 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Unregister callback function */
|
||
|
|
_gpio_instances[gpio_port].callback[gpio_pin % 16] = NULL;
|
||
|
|
/* Set the bit corresponding to the gpio pin */
|
||
|
|
_gpio_instances[gpio_port].callback_reg_mask &= ~(1 << (gpio_pin % 16));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Enables callback
|
||
|
|
*
|
||
|
|
* Enables the callback function registered by the \ref gpio_register_callback.
|
||
|
|
* The callback function will be called from the interrupt handler when the
|
||
|
|
* conditions for the callback type are met.
|
||
|
|
*
|
||
|
|
* \param[in] gpio_pin GPIO pin
|
||
|
|
*/
|
||
|
|
void gpio_enable_callback(uint8_t gpio_pin)
|
||
|
|
{
|
||
|
|
Assert(gpio_pin < 48);
|
||
|
|
|
||
|
|
uint8_t gpio_port = 0;
|
||
|
|
|
||
|
|
if (gpio_pin < 16) {
|
||
|
|
gpio_port = 0;
|
||
|
|
NVIC_EnableIRQ(GPIO0_IRQn);
|
||
|
|
} else if (gpio_pin < 32) {
|
||
|
|
gpio_port = 1;
|
||
|
|
NVIC_EnableIRQ(GPIO1_IRQn);
|
||
|
|
} else {
|
||
|
|
gpio_port = 2;
|
||
|
|
NVIC_EnableIRQ(GPIO2_IRQn);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable callback */
|
||
|
|
_gpio_instances[gpio_port].callback_enable_mask |= (1 << (gpio_pin % 16));
|
||
|
|
_gpio_instances[gpio_port].hw->INTENSET.reg = (1 << (gpio_pin % 16));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief Disables callback
|
||
|
|
*
|
||
|
|
* Disables the callback function registered by the \ref usart_register_callback.
|
||
|
|
* The callback function will not be called from the interrupt handler.
|
||
|
|
*
|
||
|
|
* \param[in] gpio_pin GPIO pin
|
||
|
|
*/
|
||
|
|
void gpio_disable_callback(uint8_t gpio_pin)
|
||
|
|
{
|
||
|
|
Assert(gpio_pin < 48);
|
||
|
|
|
||
|
|
uint8_t gpio_port = 0;
|
||
|
|
|
||
|
|
if (gpio_pin < 16) {
|
||
|
|
gpio_port = 0;
|
||
|
|
} else if (gpio_pin < 32) {
|
||
|
|
gpio_port = 1;
|
||
|
|
} else {
|
||
|
|
gpio_port = 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable callback */
|
||
|
|
_gpio_instances[gpio_port].callback_enable_mask &= ~(1 << (gpio_pin % 16));
|
||
|
|
_gpio_instances[gpio_port].hw->INTENCLR.reg = (1 << (gpio_pin % 16));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \internal GPIO port0 isr handler.
|
||
|
|
*
|
||
|
|
* This function will enter interrupt.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
static void gpio_port0_isr_handler(void)
|
||
|
|
{
|
||
|
|
uint32_t flag = _gpio_instances[0].hw->INTSTATUSCLEAR.reg;
|
||
|
|
|
||
|
|
for (uint8_t i = 0; i < 16; i++){
|
||
|
|
if (flag & (1 << i)) {
|
||
|
|
/* Clear interrupt flag */
|
||
|
|
_gpio_instances[0].hw->INTSTATUSCLEAR.reg = (1 << i);
|
||
|
|
if ((_gpio_instances[0].callback_enable_mask & (1 << i)) && \
|
||
|
|
(_gpio_instances[0].callback_reg_mask & (1 << i)))
|
||
|
|
_gpio_instances[0].callback[i]();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
NVIC_ClearPendingIRQ(GPIO0_IRQn);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \internal GPIO port1 isr handler.
|
||
|
|
*
|
||
|
|
* This function will enter interrupt.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
static void gpio_port1_isr_handler(void)
|
||
|
|
{
|
||
|
|
uint32_t flag = _gpio_instances[1].hw->INTSTATUSCLEAR.reg;
|
||
|
|
|
||
|
|
for (uint8_t i = 0; i < 16; i++){
|
||
|
|
/* For AON wakeup pin clear interrupt */
|
||
|
|
if (flag & ((1<<15) | (1<<14) | (1<<13))) {
|
||
|
|
aon_handle_ext_wakeup_isr();
|
||
|
|
}
|
||
|
|
|
||
|
|
if (flag & (1 << i)) {
|
||
|
|
/* Clear interrupt flag */
|
||
|
|
_gpio_instances[1].hw->INTSTATUSCLEAR.reg = (1 << i);
|
||
|
|
if ((_gpio_instances[1].callback_enable_mask & (1 << i)) && \
|
||
|
|
(_gpio_instances[1].callback_reg_mask & (1 << i))) {
|
||
|
|
_gpio_instances[1].callback[i]();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
NVIC_ClearPendingIRQ(GPIO1_IRQn);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \internal GPIO port2 isr handler.
|
||
|
|
*
|
||
|
|
* This function will enter interrupt.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
static void gpio_port2_isr_handler(void)
|
||
|
|
{
|
||
|
|
uint32_t flag = _gpio_instances[2].hw->INTSTATUSCLEAR.reg;
|
||
|
|
|
||
|
|
for (uint8_t i = 12; i < 16; i++){
|
||
|
|
if (flag & (1 << i)) {
|
||
|
|
/* Clear interrupt flag */
|
||
|
|
_gpio_instances[2].hw->INTSTATUSCLEAR.reg = (1 << i);
|
||
|
|
if ((_gpio_instances[2].callback_enable_mask & (1 << i)) && \
|
||
|
|
(_gpio_instances[2].callback_reg_mask & (1 << i)))
|
||
|
|
_gpio_instances[2].callback[i]();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
NVIC_ClearPendingIRQ(GPIO2_IRQn);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \internal GPIO callback init.
|
||
|
|
*
|
||
|
|
* This function will init GPIO callback.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void gpio_init(void)
|
||
|
|
{
|
||
|
|
uint8_t i, j;
|
||
|
|
|
||
|
|
for(i = 0; i < 3; i++) {
|
||
|
|
for(j = 0; j < 16; j++) {
|
||
|
|
_gpio_instances[i].callback[j] = NULL;
|
||
|
|
}
|
||
|
|
_gpio_instances[i].callback_enable_mask = 0;
|
||
|
|
_gpio_instances[i].callback_reg_mask = 0;
|
||
|
|
}
|
||
|
|
_gpio_instances[0].hw = (void *)GPIO0;
|
||
|
|
_gpio_instances[1].hw = (void *)GPIO1;
|
||
|
|
_gpio_instances[2].hw = (void *)GPIO2;
|
||
|
|
system_register_isr(RAM_ISR_TABLE_PORT0_COMB_INDEX, (uint32_t)gpio_port0_isr_handler);
|
||
|
|
system_register_isr(RAM_ISR_TABLE_PORT1_COMB_INDEX, (uint32_t)gpio_port1_isr_handler);
|
||
|
|
system_register_isr(RAM_ISR_TABLE_PORT2_COMB_INDEX, (uint32_t)gpio_port2_isr_handler);
|
||
|
|
}
|
||
|
|
|