475 lines
13 KiB
C
475 lines
13 KiB
C
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#include <rtdevice.h>
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#include "gtypes.h"
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#include "gh_uart.h"
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#include "gh_debug_rct.h"
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#include "gd_uart.h"
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#include "gd_int.h"
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/*---------------------------------------------------------------------------*/
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/* local defines */
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/*---------------------------------------------------------------------------*/
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#define UART_IRQ_CLEAR_ALL 0x3 /* IRQ CLR Register: rx_IRQ, rx_parity_IRQ */
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#define UART_RISING_TXE_RXE 0x3 /* for UART_control register: */
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/* clock edge polarity = rising, */
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/* TX = enable, RX = enable */
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/* UART[x]_FC_REG */
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#define UART_FC_RX_ONECHAR 0x0 /* RCVR_Trigger: FIFO has 1 char */
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#define UART_FC_RX_QUARTER_FULL 0x1 /* RCVR_Trigger: FIFO is one-fourth to full */
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#define UART_FC_RX_HALF_FULL 0x2 /* RCVR_Trigger: FIFO is half to full */
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#define UART_FC_RX_2_TO_FULL 0x3 /* RCVR_Trigger: FIFO is 2 char to full */
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#define UART_FC_TX_EMPTY 0x0 /* TX_Empty_Trigger: FIFO is empty */
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#define UART_FC_TX_2_IN_FIFO 0x1 /* TX_Empty_Trigger: FIFO has 2 char */
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#define UART_FC_TX_QUATER_IN_FIFO 0x2 /* TX_Empty_Trigger: FIFO is one-fourth to full */
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#define UART_FC_TX_HALF_IN_FIFO 0x3 /* TX_Empty_Trigger: FIFO is half to full */
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/* UART[x]_II_REG */
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#define UART_II_MODEM_STATUS_CHANGED 0x0
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#define UART_II_NO_INT_PENDING 0x1
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#define UART_II_THR_EMPTY 0x2
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#define UART_II_RCV_DATA_AVAIL 0x4
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#define UART_II_RCV_STATUS 0x6
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#define UART_II_CHAR_TIMEOUT 0xc
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#define MAX_UART_CNT (3)
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/*---------------------------------------------------------------------------*/
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/* local data types */
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/*---------------------------------------------------------------------------*/
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struct gk_uart
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{
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u8 index;
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};
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/*---------------------------------------------------------------------------*/
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/* local data */
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/*---------------------------------------------------------------------------*/
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static struct gk_uart uart[MAX_UART_CNT] =
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{
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{0},{1},{2}
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};
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static GD_HANDLE intHandle[MAX_UART_CNT];
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static struct rt_serial_device serial[MAX_UART_CNT];
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/*---------------------------------------------------------------------------*/
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/* local functions */
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/*---------------------------------------------------------------------------*/
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static void uartSetBaudrate(U32 index, U32 baudRate)
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{
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U32 brdi;
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GH_PLL_set_SCALER_UART(0x01);
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brdi = (48000000/2) * 10 / baudRate / 16;
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if (brdi % 10 >= 5)
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brdi = (brdi / 10) + 1;
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else
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brdi = (brdi / 10);
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GH_UART_set_LCR_dlab(index, 1);
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GH_UART_set_DLL_BaudDivint_L(index, brdi & 0xff);
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GH_UART_set_DLH_BaudDivint_H(index, (brdi >> 8) & 0xff);
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GH_UART_set_LCR_dlab(index, 0);
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}
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static void uartSetDataBits(U32 index, U32 dataBits)
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{
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U32 data_bits = dataBits;
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// 0 = use 5 data bits
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// 1 = use 6 data bits
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// 2 = use 7 data bits
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// 3 = use 8 data bits
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//data_bits -= GD_UART_5_DATATBITS;
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if(GH_UART_get_LCR_cls(index) != data_bits)
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{
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GH_UART_set_LCR_cls(index, data_bits);
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}
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}
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static void uartSetStopBits(U32 index, U32 stopBits)
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{
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// 0 = use 1 stop bit
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// 1 = use 2 stop bits
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if(GH_UART_get_LCR_stop(index) != stopBits)
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{
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GH_UART_set_LCR_stop(index, stopBits);
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}
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}
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static void uartSetParity(U32 index, U32 parity)
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{
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switch(parity)
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{
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case GD_UART_NO_PARITY:
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if(GH_UART_get_LCR_pen(index))
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{
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GH_UART_set_LCR_pen(index, 0);
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}
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break;
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case GD_UART_ODD_PARITY:
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if(!GH_UART_get_LCR_pen(index))
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{
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GH_UART_set_LCR_pen(index, 1);
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}
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if(GH_UART_get_LCR_eps(index))
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{
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GH_UART_set_LCR_eps(index, 0);
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}
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break;
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case GD_UART_EVEN_PARITY:
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if(!GH_UART_get_LCR_pen(index))
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{
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GH_UART_set_LCR_pen(index, 1);
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}
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if(!GH_UART_get_LCR_eps(index))
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{
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GH_UART_set_LCR_eps(index, 1);
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}
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break;
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default:
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break;
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}
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}
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static void uartSetFlowControl(U32 index, U32 flowCtrl)
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{
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if(index == 0)
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{
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// In UART0, only the Loopback bit is used and flow control is not supported.
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// In UART1, all the bits are used.
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if((flowCtrl == 0) || (flowCtrl == 0x10))
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{
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if(GH_UART_get_MCR(index) != flowCtrl)
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{
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GH_UART_set_MCR(index, flowCtrl);
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}
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}
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return;
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}
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if(GH_UART_get_MCR(index) != flowCtrl)
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{
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GH_UART_set_MCR(index, flowCtrl);
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}
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}
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static void uartISR(void)
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{
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U8 interruptID;
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interruptID = GH_UART_get_IIR_interrupt_id(0);
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switch (interruptID)
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{
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case UART_II_MODEM_STATUS_CHANGED:
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case UART_II_NO_INT_PENDING:
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break;
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case UART_II_THR_EMPTY:
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rt_hw_serial_isr(&serial[0], RT_SERIAL_EVENT_TX_DONE);
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break;
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case UART_II_RCV_DATA_AVAIL:
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case UART_II_RCV_STATUS:
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rt_hw_serial_isr(&serial[0], RT_SERIAL_EVENT_RX_IND);
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break;
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case UART_II_CHAR_TIMEOUT:
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GH_UART_get_RBR_Data(0);
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rt_hw_serial_isr(&serial[0], RT_SERIAL_EVENT_RX_TIMEOUT);
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break;
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default:
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break;
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}
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}
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static void uartISR1(void)
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{
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U8 interruptID;
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interruptID = GH_UART_get_IIR_interrupt_id(1);
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switch (interruptID)
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{
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case UART_II_MODEM_STATUS_CHANGED:
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case UART_II_NO_INT_PENDING:
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break;
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case UART_II_THR_EMPTY:
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rt_hw_serial_isr(&serial[1], RT_SERIAL_EVENT_TX_DONE);
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break;
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case UART_II_RCV_DATA_AVAIL:
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case UART_II_RCV_STATUS:
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rt_hw_serial_isr(&serial[1], RT_SERIAL_EVENT_RX_IND);
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break;
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case UART_II_CHAR_TIMEOUT:
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GH_UART_get_RBR_Data(1);
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rt_hw_serial_isr(&serial[1], RT_SERIAL_EVENT_RX_TIMEOUT);
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break;
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default:
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break;
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}
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}
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static void uartISR2(void)
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{
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U8 interruptID;
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interruptID = GH_UART_get_IIR_interrupt_id(2);
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switch (interruptID)
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{
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case UART_II_MODEM_STATUS_CHANGED:
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case UART_II_NO_INT_PENDING:
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break;
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case UART_II_THR_EMPTY:
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rt_hw_serial_isr(&serial[2], RT_SERIAL_EVENT_TX_DONE);
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break;
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case UART_II_RCV_DATA_AVAIL:
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case UART_II_RCV_STATUS:
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rt_hw_serial_isr(&serial[2], RT_SERIAL_EVENT_RX_IND);
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break;
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case UART_II_CHAR_TIMEOUT:
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GH_UART_get_RBR_Data(2);
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rt_hw_serial_isr(&serial[2], RT_SERIAL_EVENT_RX_TIMEOUT);
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break;
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default:
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break;
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}
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}
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static GERR uartSetIntMode(U8 channel)
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{
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GD_UART_STATE_MACHINE_S* uart_handle_ptr = NULL;
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GD_INT_OPEN_PARAMS_S intParams;
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GERR ret = GD_OK;
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intParams.sensitivity = GD_INT_LEVEL_HIGH; //hhl note: check this value.
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intParams.active = GD_INT_INVERT_IRQ;
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intParams.priority = GD_INT_MID_PRIORITY;
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if(channel == 0)
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{
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intParams.type = (S8)GD_INT_UART_IRQ;
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intParams.isrFct.lowPrio = uartISR;
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ret = GD_INT_Open(&intParams, &intHandle[0]);
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}
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else if(channel == 1)
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{
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intParams.type = (S8)GD_INT_UART1_IRQ;
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intParams.isrFct.lowPrio = uartISR1;
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ret = GD_INT_Open(&intParams, &intHandle[1]);
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}
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else
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{
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intParams.type = (S8)GD_INT_UART2_IRQ;
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intParams.isrFct.lowPrio = uartISR2;
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ret = GD_INT_Open(&intParams, &intHandle[2]);
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}
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return ret;
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}
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/**
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* UART device in RT-Thread
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*/
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static rt_err_t gk_uart_configure(struct rt_serial_device *serial,
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struct serial_configure *cfg)
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{
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int div;
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GD_UART_DATABITS_E data_mode;
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GD_UART_STOPBITS_E stop_mode;
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GD_UART_PARITY_E parity_mode;
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struct gk_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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uart = (struct gk_uart *)serial->parent.user_data;
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switch (cfg->data_bits)
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{
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case DATA_BITS_8:
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data_mode = GD_UART_8_DATATBITS;
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break;
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case DATA_BITS_7:
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data_mode = GD_UART_7_DATATBITS;
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break;
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case DATA_BITS_6:
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data_mode = GD_UART_6_DATATBITS;
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break;
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case DATA_BITS_5:
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data_mode = GD_UART_5_DATATBITS;
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break;
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default:
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data_mode = GD_UART_8_DATATBITS;
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break;
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}
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switch (cfg->stop_bits)
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{
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case STOP_BITS_2:
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stop_mode = GD_UART_20_STOPBITS;//UART_STOP_BIT2;
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break;
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case STOP_BITS_1:
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default:
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stop_mode = GD_UART_10_STOPBITS;
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break;
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}
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switch (cfg->parity)
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{
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case PARITY_ODD:
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parity_mode = GD_UART_ODD_PARITY;
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break;
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case PARITY_EVEN:
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parity_mode = GD_UART_EVEN_PARITY;
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break;
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case PARITY_NONE:
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default:
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parity_mode = GD_UART_NO_PARITY;
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break;
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}
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uartSetBaudrate(uart->index,cfg->baud_rate);
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uartSetDataBits(uart->index, data_mode);
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uartSetParity(uart->index, parity_mode);
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uartSetStopBits(uart->index, stop_mode);
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uartSetFlowControl(uart->index,0);
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return RT_EOK;
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}
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#define RT_DEVICE_CTRL_GET_CONFIG 0xFF
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static rt_err_t gk_uart_control(struct rt_serial_device *serial,
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int cmd, void *arg)
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{
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struct gk_uart* uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct gk_uart *)serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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GD_INT_Enable(&intHandle[uart->index],0);
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GH_UART_set_IER_erbfi(uart->index, 0);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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GH_UART_set_FCR_FIFO_Enable(uart->index, 1);
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GH_UART_set_FCR_RCVR_Trigger(uart->index, UART_FC_RX_ONECHAR);
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GH_UART_set_FCR_TX_Empty_Trigger(uart->index, UART_FC_TX_EMPTY);
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GH_UART_set_FCR_XMIT_FIFO_Reset(uart->index, 1);
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GH_UART_set_FCR_RCVR_FIFO_Reset(uart->index, 1);
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GH_UART_set_IER_etbei(uart->index, 0); //Turn off THRE interrupt
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|
||
|
|
uartSetIntMode(uart->index);
|
||
|
|
|
||
|
|
GD_INT_Enable(&intHandle[uart->index],1);
|
||
|
|
|
||
|
|
GH_UART_set_IER_erbfi(uart->index,1);
|
||
|
|
GH_UART_set_IER_elsi(uart->index,1);
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case RT_DEVICE_CTRL_GET_CONFIG:
|
||
|
|
if(!arg)
|
||
|
|
{
|
||
|
|
rt_kprintf("%s,line=%d,param is NULL!\n",__FUNCTION__,__LINE__);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
*((struct serial_configure *)arg) = serial->config;
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int gk_uart_putc(struct rt_serial_device *serial, char c)
|
||
|
|
{
|
||
|
|
struct gk_uart *uart = serial->parent.user_data;
|
||
|
|
unsigned int ret;
|
||
|
|
ret = GH_UART_get_LSR_temt(uart->index);
|
||
|
|
|
||
|
|
if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){
|
||
|
|
|
||
|
|
GH_UART_set_THR_Data(uart->index, c);
|
||
|
|
if (GH_UART_get_IER_etbei(uart->index) == 0)
|
||
|
|
{
|
||
|
|
GH_UART_set_IER_etbei(uart->index, 1); //Turn on THRE interrupt
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
while(!GH_UART_get_LSR_temt(uart->index));
|
||
|
|
GH_UART_set_THR_Data(uart->index, c);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static int gk_uart_getc(struct rt_serial_device *serial)
|
||
|
|
{
|
||
|
|
struct gk_uart *uart = serial->parent.user_data;
|
||
|
|
|
||
|
|
if(!GH_UART_get_LSR_dr(uart->index))
|
||
|
|
return -1;
|
||
|
|
|
||
|
|
return GH_UART_get_RBR_Data(uart->index);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_uart_ops gk_uart_ops =
|
||
|
|
{
|
||
|
|
gk_uart_configure,
|
||
|
|
gk_uart_control,
|
||
|
|
gk_uart_putc,
|
||
|
|
gk_uart_getc,
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This function will handle init uart
|
||
|
|
*/
|
||
|
|
void rt_hw_uart_init(void)
|
||
|
|
{
|
||
|
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||
|
|
int i;
|
||
|
|
char devname[6];
|
||
|
|
|
||
|
|
for(i=0; i<MAX_UART_CNT; i++)
|
||
|
|
{
|
||
|
|
serial[i].ops = &gk_uart_ops;
|
||
|
|
serial[i].config = config;
|
||
|
|
|
||
|
|
rt_sprintf(devname,"uart%d",i);
|
||
|
|
|
||
|
|
rt_hw_serial_register(&serial[i], devname,
|
||
|
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STREAM ,
|
||
|
|
&uart[i]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
int GM_Printf(const char *__format, ...)
|
||
|
|
{
|
||
|
|
rt_kprintf(__format);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|