2022-07-07 17:12:56 +08:00
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/* generated vector header file - do not edit */
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#ifndef VECTOR_DATA_H
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#define VECTOR_DATA_H
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/* Number of interrupts allocated */
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#ifndef VECTOR_DATA_IRQ_COUNT
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2024-04-15 17:13:10 +08:00
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#define VECTOR_DATA_IRQ_COUNT (4)
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2022-07-07 17:12:56 +08:00
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#endif
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/* ISR prototypes */
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void sci_uart_rxi_isr(void);
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void sci_uart_txi_isr(void);
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void sci_uart_tei_isr(void);
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void sci_uart_eri_isr(void);
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/* Vector table allocations */
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#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */
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#define SCI9_RXI_IRQn ((IRQn_Type) 4) /* SCI9 RXI (Received data full) */
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#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 5) /* SCI9 TXI (Transmit data empty) */
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#define SCI9_TXI_IRQn ((IRQn_Type) 5) /* SCI9 TXI (Transmit data empty) */
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#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 6) /* SCI9 TEI (Transmit end) */
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#define SCI9_TEI_IRQn ((IRQn_Type) 6) /* SCI9 TEI (Transmit end) */
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#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 7) /* SCI9 ERI (Receive error) */
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#define SCI9_ERI_IRQn ((IRQn_Type) 7) /* SCI9 ERI (Receive error) */
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#endif /* VECTOR_DATA_H */
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