241 lines
8.9 KiB
C
241 lines
8.9 KiB
C
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/*******************************************************************************
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* Copyright (C) 2013 Spansion LLC. All Rights Reserved.
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*
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* This software is owned and published by:
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* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion").
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*
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* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
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* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
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*
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* This software contains source code for use with Spansion
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* components. This software is licensed by Spansion to be adapted only
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* for use in systems utilizing Spansion components. Spansion shall not be
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* responsible for misuse or illegal use of this software for devices not
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* supported herein. Spansion is providing this software "AS IS" and will
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* not be responsible for issues arising from incorrect user implementation
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* of the software.
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*
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* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
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* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
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* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
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* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
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* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
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* WARRANTY OF NONINFRINGEMENT.
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* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
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* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
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* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
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* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
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* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
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* SAVINGS OR PROFITS,
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* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
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* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
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* FROM, THE SOFTWARE.
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*
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* This software may be replicated in part or whole for the licensed use,
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* with the restriction that this Disclaimer and Copyright notice must be
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* included with each copy of this software, whether used in part or whole,
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* at all times.
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*/
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/**
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******************************************************************************
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** \file system_mb9abxxx.c
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**
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** FM3 system initialization functions
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** All adjustments can be done in belonging header file.
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**
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** History:
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** 2013-01-21 0.1 MWi AI: Unification to be done
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** 2013-01-23 0.2 MWi mcu.h inclusion changed to pdl.h
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** 2013-06-28 0.3 EH Added Trace Buffer enable
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******************************************************************************/
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#include "mcu.h"
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/**
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******************************************************************************
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** System Clock Frequency (Core Clock) Variable according CMSIS
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******************************************************************************/
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uint32_t SystemCoreClock = __HCLK;
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/**
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******************************************************************************
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** \brief Update the System Core Clock with current core Clock retrieved from
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** cpu registers.
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** \param none
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** \return none
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******************************************************************************/
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void SystemCoreClockUpdate (void) {
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uint32_t masterClk;
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uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
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switch ((FM4_CRG->SCM_CTL >> 5U) & 0x07U) {
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case 0u: /* internal High-speed Cr osc. */
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masterClk = __CLKHC;
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break;
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case 1u: /* external main osc. */
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masterClk = __CLKMO;
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break;
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case 2u: /* PLL clock */
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// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
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// violation:
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// "Unordered accesses to a volatile location"
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u32RegisterRead = (__CLKMO * (((uint32_t)(FM4_CRG->PLL_CTL2) & 0x3Fu) + 1u));
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masterClk = (u32RegisterRead / ((((uint32_t)(FM4_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u));
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break;
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case 4u: /* internal Low-speed CR osc. */
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masterClk = __CLKLC;
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break;
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case 5u: /* external Sub osc. */
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masterClk = __CLKSO;
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break;
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default:
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masterClk = 0ul;
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break;
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}
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switch (FM4_CRG->BSC_PSR & 0x07u) {
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case 0u:
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SystemCoreClock = masterClk;
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break;
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case 1u:
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SystemCoreClock = masterClk / 2u;
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break;
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case 2u:
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SystemCoreClock = masterClk / 3u;
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break;
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case 3u:
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SystemCoreClock = masterClk / 4u;
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break;
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case 4u:
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SystemCoreClock = masterClk / 6u;
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break;
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case 5u:
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SystemCoreClock = masterClk /8u;
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break;
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case 6u:
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SystemCoreClock = masterClk /16u;
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break;
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default:
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SystemCoreClock = 0ul;
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break;
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}
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}
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/**
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******************************************************************************
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** \brief Setup the microcontroller system. Initialize the System and update
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** the SystemCoreClock variable.
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**
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** \param none
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** \return none
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******************************************************************************/
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void SystemInit (void) {
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static uint8_t u8IoRegisterRead; // Workaround variable for MISRA C rule conformance
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#if (HWWD_DISABLE) /* HW Watchdog Disable */
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FM4_HWWDT->WDG_LCK = 0x1ACCE551u; /* HW Watchdog Unlock */
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FM4_HWWDT->WDG_LCK = 0xE5331AAEu;
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FM4_HWWDT->WDG_CTL = 0u; /* HW Watchdog stop */
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#endif
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#if (TRACE_BUFFER_ENABLE)
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FM4_FLASH_IF->FBFCR = 0x01; /* Trace Buffer enable */
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#endif
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#if (CLOCK_SETUP) /* Clock Setup */
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FM4_CRG->BSC_PSR = (uint8_t)BSC_PSR_Val; /* set System Clock presacaler */
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FM4_CRG->APBC0_PSR = (uint8_t)APBC0_PSR_Val; /* set APB0 presacaler */
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FM4_CRG->APBC1_PSR = (uint8_t)APBC1_PSR_Val; /* set APB1 presacaler */
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FM4_CRG->APBC2_PSR = (uint8_t)APBC2_PSR_Val; /* set APB2 presacaler */
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FM4_CRG->SWC_PSR = (uint8_t)(SWC_PSR_Val | (1ul << 7u)); /* set SW Watchdog presacaler */
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FM4_CRG->TTC_PSR = (uint8_t)TTC_PSR_Val; /* set Trace Clock presacaler */
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FM4_CRG->CSW_TMR = (uint8_t)CSW_TMR_Val; /* set oscillation stabilization wait time */
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if (SCM_CTL_Val & (1ul << 1u)) { /* Main clock oscillator enabled ? */
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FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 1u); /* enable main oscillator */
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while (!((FM4_CRG->SCM_STR) & (uint8_t)(1ul << 1u))) /* wait for Main clock oscillation stable */
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{}
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}
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if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
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// Initialize VBAT (Temporary process)
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FM4_RTC->VDET = 0x00;
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FM4_RTC->VBPFR = 0x1C;
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FM4_RTC->CCB = 0x10;
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FM4_RTC->CCS = 0x08;
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// VB_CLK is less or equal to 1MHz (Temporary process)
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FM4_RTC->VB_CLKDIV = 0x4E;
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FM4_RTC->BOOST = 0x03;
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// Enable SUB CLK oscilation (Temporary process)
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FM4_RTC->WTOSCCNT_f.SOSCEX = 0;
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FM4_RTC->WTOSCCNT_f.SOSCNTL = 1;
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// Transmit to VBAT domain (Temporary process)
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FM4_RTC->WTCR20_f.PWRITE = 1;
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// Wait to complete transmission
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while(0 != FM4_RTC->WTCR10_f.TRANS)
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FM4_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
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while (!(FM4_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
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}
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FM4_CRG->PSW_TMR = (uint8_t)PSW_TMR_Val; /* set PLL stabilization wait time */
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FM4_CRG->PLL_CTL1 = (uint8_t) PLL_CTL1_Val; /* set PLLM and PLLK */
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FM4_CRG->PLL_CTL2 = (uint8_t)PLL_CTL2_Val; /* set PLLN */
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if (SCM_CTL_Val & (uint8_t)(1ul << 4u)) { /* PLL enabled ? */
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FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 4u); /* enable PLL */
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while (!(FM4_CRG->SCM_STR & (uint8_t)(1ul << 4u))) /* wait for PLL stable */
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{}
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}
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FM4_CRG->SCM_CTL |= (uint8_t)(SCM_CTL_Val & 0xE0u); /* Set Master Clock switch */
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// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
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// violations:
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// "Unordered reads and writes to or from same location" and
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// "Unordered accesses to a volatile location"
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do
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{
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u8IoRegisterRead = (FM4_CRG->SCM_CTL & 0xE0u);
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}while ((FM4_CRG->SCM_STR & 0xE0u) != u8IoRegisterRead);
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#endif // (CLOCK_SETUP)
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#if (CR_TRIM_SETUP)
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/* CR Trimming Data */
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if( 0x000003FFu != (FM4_FLASH_IF->CRTRMM & 0x000003FFu) )
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{
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/* UnLock (MCR_FTRM) */
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FM4_CRTRIM->MCR_RLR = (uint32_t)0x1ACCE554u;
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/* Set MCR_FTRM */
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FM4_CRTRIM->MCR_FTRM = (uint16_t)FM4_FLASH_IF->CRTRMM;
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/* Lock (MCR_FTRM) */
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FM4_CRTRIM->MCR_RLR = (uint32_t)0x00000000u;
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}
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#endif // (CR_TRIM_SETUP)
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}
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