312 lines
9.7 KiB
Plaintext
312 lines
9.7 KiB
Plaintext
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/*********************************************************************
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* SEGGER MICROCONTROLLER GmbH & Co. K.G. *
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* Solutions for real time microcontroller applications *
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**********************************************************************
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* *
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* (c) 2011-2015 SEGGER Microcontroller GmbH & Co. KG *
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* *
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* Internet: www.segger.com Support: support@segger.com *
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* *
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**********************************************************************
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----------------------------------------------------------------------
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Purpose :
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---------------------------END-OF-HEADER------------------------------
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*/
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void Clock_Init() {
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// Enable all clocks
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MEM_WriteU32(0x400FC068,0xffffffff);
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MEM_WriteU32(0x400FC06C,0xffffffff);
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MEM_WriteU32(0x400FC070,0xffffffff);
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MEM_WriteU32(0x400FC074,0xffffffff);
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MEM_WriteU32(0x400FC078,0xffffffff);
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MEM_WriteU32(0x400FC07C,0xffffffff);
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MEM_WriteU32(0x400FC080,0xffffffff);
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MEM_WriteU32(0x400D8030,0x00002001);
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MEM_WriteU32(0x400D8100,0x00100000);
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MEM_WriteU32(0x400FC014,0x00050D40);
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Report("Clock Init Done");
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}
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void SDRAM_WaitIpCmdDone(void)
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{
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unsigned int reg;
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do
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{
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reg = MEM_ReadU32(0x402F003C);
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}while((reg & 0x3) == 0);
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}
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void SDRAM_Init() {
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// Config IOMUX for SDRAM
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MEM_WriteU32(0x401F8014,0x00000000);
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MEM_WriteU32(0x401F8018,0x00000000);
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MEM_WriteU32(0x401F801C,0x00000000);
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MEM_WriteU32(0x401F8020,0x00000000);
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MEM_WriteU32(0x401F8024,0x00000000);
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MEM_WriteU32(0x401F8028,0x00000000);
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MEM_WriteU32(0x401F802C,0x00000000);
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MEM_WriteU32(0x401F8030,0x00000000);
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MEM_WriteU32(0x401F8034,0x00000000);
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MEM_WriteU32(0x401F8038,0x00000000);
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MEM_WriteU32(0x401F803C,0x00000000);
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MEM_WriteU32(0x401F8040,0x00000000);
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MEM_WriteU32(0x401F8044,0x00000000);
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MEM_WriteU32(0x401F8048,0x00000000);
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MEM_WriteU32(0x401F804C,0x00000000);
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MEM_WriteU32(0x401F8050,0x00000000);
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MEM_WriteU32(0x401F8054,0x00000000);
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MEM_WriteU32(0x401F8058,0x00000000);
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MEM_WriteU32(0x401F805C,0x00000000);
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MEM_WriteU32(0x401F8060,0x00000000);
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MEM_WriteU32(0x401F8064,0x00000000);
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MEM_WriteU32(0x401F8068,0x00000000);
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MEM_WriteU32(0x401F806C,0x00000000);
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MEM_WriteU32(0x401F8070,0x00000000);
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MEM_WriteU32(0x401F8074,0x00000000);
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MEM_WriteU32(0x401F8078,0x00000000);
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MEM_WriteU32(0x401F807C,0x00000000);
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MEM_WriteU32(0x401F8080,0x00000000);
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MEM_WriteU32(0x401F8084,0x00000000);
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MEM_WriteU32(0x401F8088,0x00000000);
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MEM_WriteU32(0x401F808C,0x00000000);
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MEM_WriteU32(0x401F8090,0x00000000);
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MEM_WriteU32(0x401F8094,0x00000000);
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MEM_WriteU32(0x401F8098,0x00000000);
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MEM_WriteU32(0x401F809C,0x00000000);
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MEM_WriteU32(0x401F80A0,0x00000000);
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MEM_WriteU32(0x401F80A4,0x00000000);
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MEM_WriteU32(0x401F80A8,0x00000000);
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MEM_WriteU32(0x401F80AC,0x00000000);
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MEM_WriteU32(0x401F80B0,0x00000000);
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MEM_WriteU32(0x401F80B4,0x00000000);
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MEM_WriteU32(0x401F80B8,0x00000000);
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// PAD ctrl
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MEM_WriteU32(0x401F8204,0x000000F1);
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MEM_WriteU32(0x401F8208,0x000000F1);
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MEM_WriteU32(0x401F820C,0x000000F1);
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MEM_WriteU32(0x401F8210,0x000000F1);
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MEM_WriteU32(0x401F8214,0x000000F1);
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MEM_WriteU32(0x401F8218,0x000000F1);
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MEM_WriteU32(0x401F821C,0x000000F1);
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MEM_WriteU32(0x401F8220,0x000000F1);
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MEM_WriteU32(0x401F8224,0x000000F1);
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MEM_WriteU32(0x401F8228,0x000000F1);
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MEM_WriteU32(0x401F822C,0x000000F1);
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MEM_WriteU32(0x401F8230,0x000000F1);
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MEM_WriteU32(0x401F8234,0x000000F1);
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MEM_WriteU32(0x401F8238,0x000000F1);
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MEM_WriteU32(0x401F823C,0x000000F1);
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MEM_WriteU32(0x401F8240,0x000000F1);
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MEM_WriteU32(0x401F8244,0x000000F1);
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MEM_WriteU32(0x401F8248,0x000000F1);
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MEM_WriteU32(0x401F824C,0x000000F1);
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MEM_WriteU32(0x401F8250,0x000000F1);
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MEM_WriteU32(0x401F8254,0x000000F1);
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MEM_WriteU32(0x401F8258,0x000000F1);
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MEM_WriteU32(0x401F825C,0x000000F1);
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MEM_WriteU32(0x401F8260,0x000000F1);
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MEM_WriteU32(0x401F8264,0x000000F1);
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MEM_WriteU32(0x401F8268,0x000000F1);
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MEM_WriteU32(0x401F826C,0x000000F1);
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MEM_WriteU32(0x401F8270,0x000000F1);
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MEM_WriteU32(0x401F8274,0x000000F1);
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MEM_WriteU32(0x401F8278,0x000000F1);
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MEM_WriteU32(0x401F827C,0x000000F1);
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MEM_WriteU32(0x401F8280,0x000000F1);
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MEM_WriteU32(0x401F8284,0x000000F1);
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MEM_WriteU32(0x401F8288,0x000000F1);
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MEM_WriteU32(0x401F828C,0x000000F1);
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MEM_WriteU32(0x401F8290,0x000000F1);
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MEM_WriteU32(0x401F8294,0x000000F1);
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MEM_WriteU32(0x401F8298,0x000000F1);
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MEM_WriteU32(0x401F829C,0x000000F1);
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MEM_WriteU32(0x401F82A0,0x000000F1);
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MEM_WriteU32(0x401F82A4,0x000000F1);
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MEM_WriteU32(0x401F82A8,0x000000F1);
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// Config SEMC
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MEM_WriteU32(0x402F0000,0x1000E000);
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MEM_WriteU32(0x402F0008,0x00030524);
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MEM_WriteU32(0x402F000C,0x06030524);
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MEM_WriteU32(0x402F0010,0x8000001B);
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MEM_WriteU32(0x402F0014,0x90000021);
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MEM_WriteU32(0x402F0004,0x00000008);
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MEM_WriteU32(0x402F0040,0x00000B27);
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MEM_WriteU32(0x402F0044,0x00100100);
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MEM_WriteU32(0x402F0048,0x00020201);
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MEM_WriteU32(0x402F004C,0x08193D0E);
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MEM_WriteU32(0x402F0080,0x00000021);
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MEM_WriteU32(0x402F0084,0x00888888);
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MEM_WriteU32(0x402F0094,0x00000002);
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MEM_WriteU32(0x402F0098,0x00000000);
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MEM_WriteU32(0x402F0090,0x80000000);
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MEM_WriteU32(0x402F009C,0xA55A000F);
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F0090,0x80000000);
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MEM_WriteU32(0x402F009C,0xA55A000C);
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F0090,0x80000000);
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MEM_WriteU32(0x402F009C,0xA55A000C);
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F00A0,0x00000022);
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MEM_WriteU32(0x402F0090,0x80000000);
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MEM_WriteU32(0x402F009C,0xA55A000A);
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SDRAM_WaitIpCmdDone();
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Report("SDRAM Init Done");
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}
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/* MPU configuration */
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void MPU_Init()
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{
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unsigned int rbar0;
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unsigned int rbar1;
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unsigned int rbar2;
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unsigned int rbar3;
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unsigned int rbar4;
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unsigned int rbar5;
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unsigned int rbar6;
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unsigned int rasr0;
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unsigned int rasr1;
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unsigned int rasr2;
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unsigned int rasr3;
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unsigned int rasr4;
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unsigned int rasr5;
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unsigned int rasr6;
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unsigned int ctrl;
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rbar0 = ((0xC0000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (0 << 0));
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rbar1 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (1 << 0));
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rbar2 = ((0x60000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (2 << 0));
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rbar3 = ((0x10000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (3 << 0));
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rbar4 = ((0x08000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (4 << 0));
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rbar5 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (5 << 0));
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rbar6 = ((0x81E00000 & ((0x7FFFFFF << 5))) | (1 << 4) | (6 << 0));
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rasr0 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0);
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rasr1 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (29 << 1) | (1 << 0);
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rasr2 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0);
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rasr3 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (27 << 1) | (1 << 0);
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rasr4 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (26 << 1) | (1 << 0);
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rasr5 = (0x3 << 24) | (3 << 16) | (0xC0 << 8) | (25 << 1) | (1 << 0);
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rasr6 = (0x3 << 24) | (1 << 19) | (0xC0 << 8) | (20 << 1) | (1 << 0);
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ctrl = (0x1 << 0) | (1 << 2);
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/* MPU_CTRL. */
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MEM_WriteU32(0xE000ED94, 0x0);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar6);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr6);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar5);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr5);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar4);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr4);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar3);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr3);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar2);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr2);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar1);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr1);
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/* MPU_RBAR. */
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MEM_WriteU32(0xE000ED9C, rbar0);
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/* MPU_RASR. */
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MEM_WriteU32(0xE000EDA0, rasr0);
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/* MPU_CTRL. */
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MEM_WriteU32(0xE000ED94, ctrl);
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}
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void flexram_init(void)
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{
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Report("flexram init\n");
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MEM_WriteU32(0x400AC040, 0x80000000); //IOMUXC_GPR_GPR16
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//MEM_WriteU32(0x400AC044, 0xFFFFAA55); //IOMUXC_GPR_GPR17: 256K ITCM, 128K DTCM, 128K OCRAM
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MEM_WriteU32(0x400AC044, 0xFFFFFFFF); //IOMUXC_GPR_GPR17: 512K ITCM
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MEM_WriteU32(0x400AC038, 0x00890000); //IOMUXC_GPR_GPR14
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MEM_WriteU32(0x400AC040, 0x80000007); //IOMUXC_GPR_GPR16
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}
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/* ConfigTarget */
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void ConfigTargetSettings(void)
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{
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Report("Config JTAG Speed to 4000kHz");
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JTAG_Speed = 4000;
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}
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/* SetupTarget */
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void SetupTarget(void) {
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Report("Enabling i.MXRT SDRAM");
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Clock_Init();
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flexram_init();
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SDRAM_Init();
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MPU_Init();
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}
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/* ResetTarget */
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void ResetTarget(void) {
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unsigned int v;
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unsigned int Tmp;
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//
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// J-Link DLL expects CPU to be reset and halted when leaving this function
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//
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Report("J-Link script: ResetTarget()");
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//issue a software reset
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//Tmp = MEM_ReadU32(0xE000ED0C);
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//Tmp = (Tmp&0x0000ffff)|0x05fa0000|(1<<2);
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//MEM_WriteU32(0xE000ED0C,Tmp);
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//SYS_Sleep(10);
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// Read IDCODE
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v=JLINK_CORESIGHT_ReadDP(0);
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Report1("DP0: ", v);
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// Power up Debugger
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JLINK_CORESIGHT_WriteDP(1, 0x50000000);
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v=JLINK_CORESIGHT_ReadDP(1);
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Report1("DP1: ", v);
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JLINK_CORESIGHT_WriteAP(0, 0x23000042);
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v=JLINK_CORESIGHT_ReadAP(0);
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Report1("AHB-AP0: ", v);
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JLINK_CORESIGHT_WriteAP(1, 0xE000EDF0);
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v=JLINK_CORESIGHT_ReadAP(1);
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Report1("AHB-AP1: ", v);
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v=JLINK_CORESIGHT_ReadAP(3);
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Report1("AHB-AP3: ", v);
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JLINK_CORESIGHT_WriteAP(3, 0xa05f0003);
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v=JLINK_CORESIGHT_ReadAP(3);
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Report1("AHB-AP3: ", v);
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|
|
||
|
|
Clock_Init();
|
||
|
|
SDRAM_Init();
|
||
|
|
MPU_Init();
|
||
|
|
}
|