2022-08-31 15:14:16 +08:00
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/**
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* @file dma_config.h
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* @author 100ask development team
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2022-08-31 22:00:02 +08:00
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* @brief
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2022-08-31 15:14:16 +08:00
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* @version 0.1
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* @date 2022-06-16
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2022-08-31 22:00:02 +08:00
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*
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2022-08-31 15:14:16 +08:00
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* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
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2022-08-31 22:00:02 +08:00
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*
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2022-08-31 15:14:16 +08:00
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 channel1 */
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#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
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#define ADC1_DMA_INSTANCE DMA1
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#define ADC1_DMA_REQ DMA_REQ_DMA1_ADC1
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#define ADC1_DMA_IRQ DMA1_CH1_IRQn
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#define ADC1_DMA_IRQHandler DMA1_Channel1_IRQHandler
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#define ADC1_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
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#define UART6_DMA_INSTANCE DMA1
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#define UART6_RX_DMA_REQ DMA_REQ_DMA1_UART6_RX
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#define UART6_RX_DMA_IRQ DMA1_CH1_IRQn
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#define UART6_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define UART6_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel2 */
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#if defined(BSP_ADC2_USING_DMA) && !defined(ADC2_DMA_INSTANCE)
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#define ADC2_DMA_INSTANCE DMA1
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#define ADC2_DMA_REQ DMA_REQ_DMA1_ADC2
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#define ADC2_DMA_IRQ DMA1_CH2_IRQn
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#define ADC2_DMA_IRQHandler DMA1_Channel2_IRQHandler
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#define ADC2_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_RX_DMA_INSTANCE DMA1
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#define SPI1_RX_DMA_REQ DMA_REQ_DMA1_SPI1_RX
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#define SPI1_RX_DMA_IRQ DMA1_CH2_IRQn
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
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#define UART3_TX_DMA_INSTANCE DMA1
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#define UART3_TX_DMA_REQ DMA_REQ_DMA1_UART3_TX
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#define UART3_TX_DMA_IRQ DMA1_CH2_IRQn
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#define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
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#define UART3_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_TX_DMA_INSTANCE DMA1
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#define SPI1_TX_DMA_REQ DMA_REQ_DMA1_SPI1_TX
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#define SPI1_TX_DMA_IRQ DMA1_CH3_IRQn
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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#define UART3_RX_DMA_INSTANCE DMA1
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#define UART3_RX_DMA_REQ DMA_REQ_DMA1_UART3_RX
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#define UART3_RX_DMA_IRQ DMA1_CH3_IRQn
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#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
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#define UART3_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel4 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_RX_DMA_INSTANCE DMA1
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#define SPI2_RX_DMA_REQ DMA_REQ_DMA1_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA1_CH4_IRQn
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_TX_DMA_INSTANCE DMA1
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#define UART1_TX_DMA_REQ DMA_REQ_DMA1_UART1_TX
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#define UART1_TX_DMA_IRQ DMA1_CH4_IRQn
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#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel5 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_TX_DMA_INSTANCE DMA1
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#define SPI2_TX_DMA_REQ DMA_REQ_DMA1_SPI2_TX
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#define SPI2_TX_DMA_IRQ DMA1_CH5_IRQn
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_RX_DMA_INSTANCE DMA1
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#define UART1_RX_DMA_REQ DMA_REQ_DMA1_UART1_RX
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#define UART1_RX_DMA_IRQ DMA1_CH5_IRQn
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#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART6_RX_DMA_INSTANCE DMA1
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#define UART6_RX_DMA_REQ DMA_REQ_DMA1_UART6_RX
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#define UART6_RX_DMA_IRQ DMA1_CH6_IRQn
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#define UART6_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
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#define UART6_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel7 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_TX_DMA_INSTANCE DMA1
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#define UART2_TX_DMA_REQ DMA_REQ_DMA1_UART2_TX
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#define UART2_TX_DMA_IRQ DMA1_CH7_IRQn
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#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA2 channel1 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_RX_DMA_INSTANCE DMA2
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#define SPI3_RX_DMA_REQ DMA_REQ_DMA2_SPI3_RX
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#define SPI3_RX_DMA_IRQ DMA2_CH1_IRQn
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#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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#define UART5_RX_DMA_INSTANCE DMA2
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#define UART5_RX_DMA_REQ DMA_REQ_DMA2_UART5_RX
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#define UART5_RX_DMA_IRQ DMA2_CH1_IRQn
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#define UART5_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define UART5_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
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#define UART7_RX_DMA_INSTANCE DMA2
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#define UART7_RX_DMA_REQ DMA_REQ_DMA2_UART7_RX
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#define UART7_RX_DMA_IRQ DMA2_CH1_IRQn
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#define UART7_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define UART7_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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/* DMA2 channel2 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_TX_DMA_INSTANCE DMA2
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#define SPI3_TX_DMA_REQ DMA_REQ_DMA2_SPI3_TX
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#define SPI3_TX_DMA_IRQ DMA2_CH2_IRQn
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#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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#define UART5_TX_DMA_INSTANCE DMA2
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#define UART5_TX_DMA_REQ DMA_REQ_DMA2_UART5_TX
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#define UART5_TX_DMA_IRQ DMA2_CH2_IRQn
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#define UART5_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define UART5_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
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#define UART7_TX_DMA_INSTANCE DMA2
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#define UART7_TX_DMA_REQ DMA_REQ_DMA2_UART7_TX
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#define UART7_TX_DMA_IRQ DMA2_CH2_IRQn
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#define UART7_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define UART7_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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/* DMA2 channel3 */
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_RX_DMA_INSTANCE DMA2
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#define UART4_RX_DMA_REQ DMA_REQ_DMA2_UART4_RX
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#define UART4_RX_DMA_IRQ DMA2_CH3_IRQn
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#define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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#define UART4_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
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#define UART8_RX_DMA_INSTANCE DMA2
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#define UART8_RX_DMA_REQ DMA_REQ_DMA2_UART8_RX
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#define UART8_RX_DMA_IRQ DMA2_CH3_IRQn
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#define UART8_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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#define UART8_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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/* DMA2 channel4 */
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#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
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#define UART6_TX_DMA_INSTANCE DMA2
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#define UART6_TX_DMA_REQ DMA_REQ_DMA2_UART6_TX
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#define UART6_TX_DMA_IRQ DMA2_CH4_IRQn
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#define UART6_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
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#define UART6_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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/* DMA2 channel5 */
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#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
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#define UART4_TX_DMA_INSTANCE DMA2
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#define UART4_TX_DMA_REQ DMA_REQ_DMA2_UART4_TX
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#define UART4_TX_DMA_IRQ DMA2_CH5_IRQn
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#define UART4_DMA_TX_IRQHandler DMA2_Channel5_IRQHandler
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#define UART4_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
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#define UART8_TX_DMA_INSTANCE DMA2
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#define UART8_TX_DMA_REQ DMA_REQ_DMA2_UART8_TX
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#define UART8_TX_DMA_IRQ DMA2_CH5_IRQn
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#define UART8_DMA_TX_IRQHandler DMA2_Channel5_IRQHandler
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#define UART8_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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