2013-01-08 22:40:58 +08:00
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/*
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2021-04-09 10:52:34 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2013-01-08 22:40:58 +08:00
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*
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2021-04-09 10:52:34 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2013-01-08 22:40:58 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2010-04-09 fify the first version
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*
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* For : Renesas M16C
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* Toolchain : IAR's EW for M16C v3.401
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*/
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;********************************************************************************************************
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; RELOCATABLE EXCEPTION VECTOR TABLE
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;********************************************************************************************************
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MODULE ?vectors
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EXTERN rt_hw_timer_handler
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EXTERN rt_hw_uart0_receive_handler
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EXTERN os_context_switch
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2021-04-09 10:52:34 +08:00
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2013-01-08 22:40:58 +08:00
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PUBLIC RelocatableVectTbl
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RSEG INTVEC:NOROOT
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RelocatableVectTbl:
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ORG 0
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DC32 os_context_switch ; Vector 0: BRK
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DC32 0 ; Vector 1: Reserved
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DC32 0 ; Vector 2: Reserved
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DC32 0 ; Vector 3: Reserved
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DC32 0 ; Vector 4: INT3
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DC32 0 ; Vector 5: Timer B5
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DC32 0 ; Vector 6: Timer B4, UART1 Bus Collision Detect
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DC32 0 ; Vector 7: Timer B3, UART0 Bus Collision Detect
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DC32 0 ; Vector 8: SI/O4, INT5
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DC32 0 ; Vector 9: SI/O3, INT4
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DC32 0 ; Vector 10: UART2 Bus Collision Detect
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DC32 0 ; Vector 11: DMA0
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DC32 0 ; Vector 12: DMA1
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DC32 0 ; Vector 13: Key Input Interrupt
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DC32 0 ; Vector 14: A/D
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DC32 0 ; Vector 15: UART2 Transmit, NACK2
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DC32 0 ; Vector 16: UART2 Receive, ACK2
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DC32 0 ; Vector 17: UART0 Transmit, NACK0
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DC32 rt_hw_uart0_receive_handler ; Vector 18: UART0 Receive, ACK0
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DC32 0 ; Vector 19: UART1 Transmit, NACK1
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DC32 0 ; Vector 20: UART1 Receive, ACK1
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DC32 0 ; Vector 21: Timer A0
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DC32 0 ; Vector 22: Timer A1
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DC32 0 ; Vector 23: Timer A2
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DC32 0 ; Vector 24: Timer A3
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DC32 0 ; Vector 25: Timer A4
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DC32 rt_hw_timer_handler ; Vector 26: Timer B0
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DC32 0 ; Vector 27: Timer B1
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DC32 0 ; Vector 28: Timer B2
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DC32 0 ; Vector 29:
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DC32 0 ; Vector 30:
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DC32 0 ; Vector 31:
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ENDMOD
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END
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