2022-10-03 15:07:07 +08:00
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-8-11 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_DISP)
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtdbg.h>
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#include "NuMicro.h"
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#include <drv_sys.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdio.h>
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#if !defined(DISP_USING_LCD_IDX)
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#define DISP_USING_LCD_IDX eDispLcd_1024x600
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#endif
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#if !defined(BSP_LCD_BPP)
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#define BSP_LCD_BPP 32
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#endif
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#if !defined(DISP_USING_OVERLAY)
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#define DISP_USING_OVERLAY
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#endif
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#define DEF_VPOST_BUFFER_NUMBER 3
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/* Private typedef --------------------------------------------------------------*/
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struct nu_disp
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{
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struct rt_device dev;
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char *name;
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E_DISP_LAYER layer;
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uint32_t last_commit;
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uint32_t ref_count;
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struct rt_device_graphic_info info;
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rt_uint8_t *pu8FBDMABuf;
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};
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typedef struct nu_disp *nu_disp_t;
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static volatile uint32_t g_u32VSyncBlank = 0;
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static struct rt_completion vsync_wq;
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2022-12-29 15:15:13 +08:00
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#if defined(DISP_USING_OVERLAY)
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static rt_mutex_t disp_lock;
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#endif
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2022-10-03 15:07:07 +08:00
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static struct nu_disp nu_fbdev[eLayer_Cnt] =
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{
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{
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.name = "lcd",
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.layer = eLayer_Video,
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.ref_count = 0,
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}
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#if defined(DISP_USING_OVERLAY)
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, {
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.name = "overlay",
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.layer = eLayer_Overlay,
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.ref_count = 0,
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}
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#endif
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};
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2022-12-29 15:15:13 +08:00
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RT_WEAK void nu_lcd_backlight_on(void) { }
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2022-10-03 15:07:07 +08:00
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2022-12-29 15:15:13 +08:00
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RT_WEAK void nu_lcd_backlight_off(void) { }
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2022-10-03 15:07:07 +08:00
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static void nu_disp_isr(int vector, void *param)
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{
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/* Get DISP INTSTS */
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if (DISP_GET_INTSTS())
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{
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g_u32VSyncBlank++;
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rt_completion_done(&vsync_wq);
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}
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}
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static rt_err_t disp_layer_open(rt_device_t dev, rt_uint16_t oflag)
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{
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nu_disp_t psDisp = (nu_disp_t)dev;
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RT_ASSERT(psDisp != RT_NULL);
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2022-12-29 15:15:13 +08:00
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#if defined(DISP_USING_OVERLAY)
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rt_mutex_take(disp_lock, RT_WAITING_FOREVER);
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#endif
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2022-10-03 15:07:07 +08:00
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psDisp->ref_count++;
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#if defined(DISP_USING_OVERLAY)
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if (psDisp->layer == eLayer_Overlay) // Depend on video layer
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{
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nu_fbdev[eLayer_Video].ref_count++;
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}
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#endif
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if (nu_fbdev[eLayer_Video].ref_count == 1)
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{
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DISP_SetTransparencyMode(eLayer_Video, eMASK);
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DISP_ENABLE_INT();
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DISP_Trigger(eLayer_Video, 1);
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}
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#if defined(DISP_USING_OVERLAY)
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if (nu_fbdev[eLayer_Overlay].ref_count == 1)
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{
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DISP_SetTransparencyMode(eLayer_Overlay, eOPAQUE);
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DISP_Trigger(eLayer_Overlay, 1);
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}
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#endif
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2022-12-29 15:15:13 +08:00
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#if defined(DISP_USING_OVERLAY)
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rt_mutex_release(disp_lock);
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#endif
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2022-10-03 15:07:07 +08:00
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return RT_EOK;
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}
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static rt_err_t disp_layer_close(rt_device_t dev)
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{
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nu_disp_t psDisp = (nu_disp_t)dev;
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RT_ASSERT(psDisp != RT_NULL);
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2022-12-29 15:15:13 +08:00
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#if defined(DISP_USING_OVERLAY)
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rt_mutex_take(disp_lock, RT_WAITING_FOREVER);
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#endif
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2022-10-03 15:07:07 +08:00
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psDisp->ref_count--;
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#if defined(DISP_USING_OVERLAY)
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if (psDisp->layer == eLayer_Overlay) // Depend on video layer
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{
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nu_fbdev[eLayer_Video].ref_count--;
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}
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if (nu_fbdev[eLayer_Overlay].ref_count == 0)
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{
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DISP_Trigger(eLayer_Overlay, 0);
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}
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#endif
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if (nu_fbdev[eLayer_Video].ref_count == 0)
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{
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DISP_DISABLE_INT();
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DISP_Trigger(eLayer_Video, 0);
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}
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2022-12-29 15:15:13 +08:00
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#if defined(DISP_USING_OVERLAY)
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rt_mutex_release(disp_lock);
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#endif
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2022-10-03 15:07:07 +08:00
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return RT_EOK;
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}
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static rt_err_t disp_layer_control(rt_device_t dev, int cmd, void *args)
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{
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nu_disp_t psDisp = (nu_disp_t)dev;
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RT_ASSERT(psDisp != RT_NULL);
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switch (cmd)
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{
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case RTGRAPHIC_CTRL_POWERON:
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{
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nu_lcd_backlight_on();
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}
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break;
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case RTGRAPHIC_CTRL_POWEROFF:
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{
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nu_lcd_backlight_off();
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}
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break;
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case RTGRAPHIC_CTRL_GET_INFO:
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{
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struct rt_device_graphic_info *info = (struct rt_device_graphic_info *) args;
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RT_ASSERT(info != RT_NULL);
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rt_memcpy(args, (void *)&psDisp->info, sizeof(struct rt_device_graphic_info));
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}
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break;
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case RTGRAPHIC_CTRL_SET_MODE:
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{
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int pixfmt, bpp;
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E_FB_FMT eFBFmt;
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RT_ASSERT(args);
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pixfmt = *((int *)args);
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switch (pixfmt)
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{
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case RTGRAPHIC_PIXEL_FORMAT_RGB565:
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eFBFmt = eFBFmt_R5G6B5;
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bpp = 16;
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break;
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case RTGRAPHIC_PIXEL_FORMAT_ARGB888:
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eFBFmt = eFBFmt_A8R8G8B8;
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bpp = 32;
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break;
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case RTGRAPHIC_PIXEL_FORMAT_MONO:
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case RTGRAPHIC_PIXEL_FORMAT_GRAY4:
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case RTGRAPHIC_PIXEL_FORMAT_GRAY16:
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case RTGRAPHIC_PIXEL_FORMAT_RGB332:
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case RTGRAPHIC_PIXEL_FORMAT_RGB444:
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case RTGRAPHIC_PIXEL_FORMAT_BGR565:
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case RTGRAPHIC_PIXEL_FORMAT_RGB666:
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case RTGRAPHIC_PIXEL_FORMAT_RGB888:
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case RTGRAPHIC_PIXEL_FORMAT_BGR888:
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case RTGRAPHIC_PIXEL_FORMAT_ABGR888:
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case RTGRAPHIC_PIXEL_FORMAT_RESERVED:
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default:
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return -RT_ERROR;
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}
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psDisp->info.bits_per_pixel = bpp;
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psDisp->info.pixel_format = pixfmt;
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psDisp->info.pitch = psDisp->info.width * (bpp >> 3U);
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/* Initial LCD */
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DISP_SetFBFmt(psDisp->layer, eFBFmt, psDisp->info.pitch);
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}
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break;
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case RTGRAPHIC_CTRL_GET_MODE:
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{
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RT_ASSERT(args);
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*((int *)args) = psDisp->info.pixel_format;
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}
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break;
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case RTGRAPHIC_CTRL_PAN_DISPLAY:
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{
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if (args != RT_NULL)
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{
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uint32_t u32BufPtr = (uint32_t)args;
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psDisp->last_commit = g_u32VSyncBlank;
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/* Pan display */
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return (DISP_SetFBAddr(psDisp->layer, u32BufPtr) == 0) ? RT_EOK : -RT_ERROR;
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}
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else
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return -RT_ERROR;
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}
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break;
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case RTGRAPHIC_CTRL_WAIT_VSYNC:
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{
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if (args != RT_NULL)
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psDisp->last_commit = g_u32VSyncBlank + 1;
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if (psDisp->last_commit >= g_u32VSyncBlank)
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{
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rt_completion_init(&vsync_wq);
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2022-12-29 15:15:13 +08:00
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rt_completion_wait(&vsync_wq, RT_TICK_PER_SECOND / DISP_LCDTIMING_GetFPS(RT_NULL));
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2022-10-03 15:07:07 +08:00
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}
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}
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break;
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default:
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static rt_err_t disp_layer_init(rt_device_t dev)
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{
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nu_disp_t psDisp = (nu_disp_t)dev;
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RT_ASSERT(psDisp != RT_NULL);
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rt_completion_init(&vsync_wq);
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return RT_EOK;
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}
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int rt_hw_disp_init(void)
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{
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int i;
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rt_err_t ret;
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/* Get LCD panel instance by ID. */
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const DISP_LCD_INFO *psDispLcdInstance = DISP_GetLCDInst(DISP_USING_LCD_IDX);
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RT_ASSERT(psDispLcdInstance != RT_NULL);
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/* Initial LCD */
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DISP_LCDInit(psDispLcdInstance);
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for (i = eLayer_Video;
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#if defined(DISP_USING_OVERLAY)
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i < eLayer_Cnt;
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#else
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i < eLayer_Overlay;
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#endif
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i++)
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{
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E_FB_FMT eFbFmt;
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nu_disp_t psDisp = &nu_fbdev[i];
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rt_memset((void *)&psDisp->info, 0, sizeof(struct rt_device_graphic_info));
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/* Register Disp device information */
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psDisp->info.bits_per_pixel = BSP_LCD_BPP;
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psDisp->info.pixel_format = (BSP_LCD_BPP == 32) ? RTGRAPHIC_PIXEL_FORMAT_ARGB888 : RTGRAPHIC_PIXEL_FORMAT_RGB565;
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psDisp->info.pitch = psDispLcdInstance->u32ResolutionWidth * (BSP_LCD_BPP / 8);
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psDisp->info.width = psDispLcdInstance->u32ResolutionWidth;
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psDisp->info.height = psDispLcdInstance->u32ResolutionHeight;
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/* Get pointer of video frame buffer */
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rt_uint8_t *pu8FBDMABuf = rt_malloc_align(psDisp->info.pitch * psDisp->info.height * DEF_VPOST_BUFFER_NUMBER, 128);
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if (pu8FBDMABuf == NULL)
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{
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rt_kprintf("Fail to get VRAM buffer for %s layer.\n", psDisp->name);
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RT_ASSERT(0);
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}
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else
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{
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/* Register non-cacheable DMA address to upper layer. */
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psDisp->info.framebuffer = (rt_uint8_t *)((uint32_t)pu8FBDMABuf | UNCACHEABLE);
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uint32_t u32FBSize = psDisp->info.pitch * psDispLcdInstance->u32ResolutionHeight;
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psDisp->info.smem_len = u32FBSize * DEF_VPOST_BUFFER_NUMBER;
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rt_memset(psDisp->info.framebuffer, 0, psDisp->info.smem_len);
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}
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eFbFmt = (psDisp->info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888) ? eFBFmt_A8R8G8B8 : eFBFmt_R5G6B5 ;
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ret = (rt_err_t)DISP_SetFBConfig(i, eFbFmt, psDisp->info.width, psDisp->info.height, (uint32_t)pu8FBDMABuf);
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RT_ASSERT(ret == RT_EOK);
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psDisp->pu8FBDMABuf = pu8FBDMABuf;
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/* Register member functions of lcd device */
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psDisp->dev.type = RT_Device_Class_Graphic;
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psDisp->dev.init = disp_layer_init;
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psDisp->dev.open = disp_layer_open;
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psDisp->dev.close = disp_layer_close;
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psDisp->dev.control = disp_layer_control;
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/* register graphic device driver */
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ret = rt_device_register(&psDisp->dev, psDisp->name, RT_DEVICE_FLAG_RDWR);
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RT_ASSERT(ret == RT_EOK);
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rt_kprintf("%s's fbdev video memory at 0x%08x.\n", psDisp->name, psDisp->info.framebuffer);
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}
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2022-12-29 15:15:13 +08:00
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#if defined(DISP_USING_OVERLAY)
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/* Initial display lock */
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disp_lock = rt_mutex_create("displock", RT_IPC_FLAG_FIFO);
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RT_ASSERT(disp_lock);
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#endif
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2022-10-03 15:07:07 +08:00
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/* Register ISR */
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rt_hw_interrupt_install(DISP_IRQn, nu_disp_isr, RT_NULL, "DISP");
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|
|
|
|
|
|
|
/* Enable interrupt. */
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|
|
|
rt_hw_interrupt_umask(DISP_IRQn);
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|
|
|
2022-12-29 15:15:13 +08:00
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|
|
rt_kprintf("LCD panel timing is %d FPS.\n", DISP_LCDTIMING_GetFPS(&psDispLcdInstance->sLcdTiming));
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|
|
|
2022-10-03 15:07:07 +08:00
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|
return (int)ret;
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|
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_disp_init);
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|
|
|
|
|
|
|
static void lcd_show_video_layer(void)
|
|
|
|
{
|
|
|
|
rt_device_open(&nu_fbdev[eLayer_Video].dev, RT_DEVICE_FLAG_RDWR);
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT(lcd_show_video_layer, show video layer);
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|
|
|
|
|
|
|
static void lcd_hide_video_layer(void)
|
|
|
|
{
|
|
|
|
rt_device_close(&nu_fbdev[eLayer_Video].dev);
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT(lcd_hide_video_layer, hide video layer);
|
|
|
|
|
|
|
|
#if defined(DISP_USING_OVERLAY)
|
|
|
|
|
|
|
|
int nu_overlay_set_colkey(uint32_t u32Low, uint32_t u32High)
|
|
|
|
{
|
|
|
|
DISP_SetColorKeyValue(u32Low, u32High);
|
|
|
|
DISP_SetTransparencyMode(eLayer_Overlay, eKEY);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
RTM_EXPORT(nu_overlay_set_colkey);
|
|
|
|
|
|
|
|
/* Support "lcd_set_overlay_colkey" command line in msh mode */
|
|
|
|
static rt_err_t lcd_set_overlay_colkey(int argc, char **argv)
|
|
|
|
{
|
|
|
|
unsigned int index, len, arg[2];
|
|
|
|
|
|
|
|
rt_memset(arg, 0, sizeof(arg));
|
|
|
|
len = (argc >= 3) ? 3 : argc;
|
|
|
|
|
|
|
|
for (index = 0; index < (len - 1); index ++)
|
|
|
|
{
|
|
|
|
if (sscanf(argv[index + 1], "%x", &arg[index]) != 1)
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
rt_kprintf("colkeylow:0x%08x colkeyhigh:0x%08x\n", arg[0], arg[1]);
|
|
|
|
nu_overlay_set_colkey(arg[0], arg[1]);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT(lcd_set_overlay_colkey, e.g: lcd_set_overlay_colkey colkeylow colkeyhigh);
|
|
|
|
|
|
|
|
static void lcd_show_overlay_layer(void)
|
|
|
|
{
|
|
|
|
rt_device_open(&nu_fbdev[eLayer_Overlay].dev, RT_DEVICE_FLAG_RDWR);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void lcd_hide_overlay_layer(void)
|
|
|
|
{
|
|
|
|
rt_device_close(&nu_fbdev[eLayer_Overlay].dev);
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT(lcd_show_overlay_layer, show overlay layer);
|
|
|
|
MSH_CMD_EXPORT(lcd_hide_overlay_layer, hide overlay layer);
|
|
|
|
|
|
|
|
static void lcd_fill_layer_color(void)
|
|
|
|
{
|
|
|
|
nu_disp_t psDispLayer;
|
|
|
|
int idx;
|
|
|
|
for (idx = eLayer_Overlay; //eLayer_Video;
|
|
|
|
#if defined(DISP_USING_OVERLAY)
|
|
|
|
idx < eLayer_Cnt;
|
|
|
|
#else
|
|
|
|
idx < eLayer_Overlay;
|
|
|
|
#endif
|
|
|
|
idx++)
|
|
|
|
{
|
|
|
|
psDispLayer = &nu_fbdev[idx];
|
|
|
|
if (psDispLayer->info.framebuffer != RT_NULL)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
uint32_t fill_num = psDispLayer->info.height * psDispLayer->info.width;
|
|
|
|
uint32_t *fbmem_start = (uint32_t *)psDispLayer->info.framebuffer;
|
|
|
|
uint32_t color = (0x3F << 24) | (rand() % 0x1000000) ;
|
|
|
|
rt_kprintf("fill color=0x%08x on %s layer\n", color, psDispLayer->name);
|
|
|
|
for (i = 0; i < fill_num; i++)
|
|
|
|
{
|
|
|
|
rt_memcpy((void *)&fbmem_start[i], &color, (psDispLayer->info.bits_per_pixel / 8));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT(lcd_fill_layer_color, fill random color on overlay layer);
|
|
|
|
|
|
|
|
static rt_err_t lcd_set_alphablend_opmode(int argc, char **argv)
|
|
|
|
{
|
|
|
|
unsigned int index, len, arg[1];
|
|
|
|
|
|
|
|
rt_memset(arg, 0, sizeof(arg));
|
|
|
|
len = (argc >= 2) ? 2 : argc;
|
|
|
|
|
|
|
|
for (index = 0; index < (len - 1); index ++)
|
|
|
|
{
|
|
|
|
if (sscanf(argv[index + 1], "%x", &arg[index]) != 1)
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt_kprintf("opmode:0x%08x\n", arg[0]);
|
|
|
|
|
|
|
|
if (arg[0] <= DC_BLEND_MODE_SRC_OUT)
|
|
|
|
DISP_SetBlendOpMode(arg[0], eGloAM_NORMAL, eGloAM_NORMAL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT(lcd_set_alphablend_opmode, Set alpha blending opmode);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif /* if defined(BSP_USING_DISP) */
|