465 lines
19 KiB
C
465 lines
19 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_adc_etc.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.adc_etc"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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#if defined(ADC_ETC_CLOCKS)
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/*!
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* @brief Get instance number for ADC_ETC module.
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*
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* @param base ADC_ETC peripheral base address
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*/
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static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to ADC_ETC bases for each instance. */
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static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to ADC_ETC clocks for each instance. */
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static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
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{
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uint32_t instance = 0U;
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uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < adcetcArrayCount; instance++)
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{
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if (s_adcetcBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < adcetcArrayCount);
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return instance;
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}
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#endif /* ADC_ETC_CLOCKS */
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/*!
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* brief Initialize the ADC_ETC module.
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*
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* param base ADC_ETC peripheral base address.
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* param config Pointer to "adc_etc_config_t" structure.
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*/
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void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32 = 0U;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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#if defined(ADC_ETC_CLOCKS)
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/* Open clock gate. */
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CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
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#endif /* ADC_ETC_CLOCKS */
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Disable software reset. */
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ADC_ETC_DoSoftwareReset(base, false);
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/* Set ADC_ETC_CTRL register. */
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tmp32 =
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
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#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
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| ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
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#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
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;
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#if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
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(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
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if (config->enableTSCBypass)
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{
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tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
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}
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#endif
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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if (config->enableTSC0Trigger)
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{
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tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK;
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}
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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if (config->enableTSC1Trigger)
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{
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tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK;
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}
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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base->CTRL = tmp32;
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}
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/*!
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* brief De-Initialize the ADC_ETC module.
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*
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* param base ADC_ETC peripheral base address.
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*/
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void ADC_ETC_Deinit(ADC_ETC_Type *base)
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{
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/* Do software reset to clear all logical. */
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ADC_ETC_DoSoftwareReset(base, true);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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#if defined(ADC_ETC_CLOCKS)
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/* Close clock gate. */
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CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
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#endif /* ADC_ETC_CLOCKS */
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Gets an available pre-defined settings for the ADC_ETC's configuration.
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* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
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* code
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* config->enableTSCBypass = true;
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* config->enableTSC0Trigger = false;
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* config->enableTSC1Trigger = false;
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* config->TSC0triggerPriority = 0U;
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* config->TSC1triggerPriority = 0U;
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* config->clockPreDivider = 0U;
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* config->XBARtriggerMask = 0U;
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* endCode
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*
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* param config Pointer to "adc_etc_config_t" structure.
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*/
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void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
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{
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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#if (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
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(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG))
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config->enableTSCBypass = true;
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#endif
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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config->enableTSC0Trigger = false;
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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config->enableTSC1Trigger = false;
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
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config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
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#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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config->TSC0triggerPriority = 0U;
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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config->TSC1triggerPriority = 0U;
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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config->clockPreDivider = 0U;
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config->XBARtriggerMask = 0U;
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}
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/*!
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* brief Set the external XBAR trigger configuration.
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*
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* param base ADC_ETC peripheral base address.
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* param triggerGroup Trigger group index.
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* param config Pointer to "adc_etc_trigger_config_t" structure.
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*/
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void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
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{
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assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
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assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup);
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uint32_t tmp32 = 0U;
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/* Set ADC_ETC_TRGn_CTRL register. */
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tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) |
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ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority);
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if (config->enableSyncMode)
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{
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tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK;
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}
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if (config->enableSWTriggerMode)
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{
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tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK;
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}
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base->TRIG[triggerGroup].TRIGn_CTRL = tmp32;
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/* Set ADC_ETC_TRGn_COUNTER register. */
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tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) |
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ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay);
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base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
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}
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/*!
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* brief Set the external XBAR trigger chain configuration.
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* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
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* configurated.
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*
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* param base ADC_ETC peripheral base address.
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* param triggerGroup Trigger group index. Available number is 0~7.
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* param chainGroup Trigger chain group index. Available number is 0~7.
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* param config Pointer to "adc_etc_trigger_chain_config_t" structure.
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*/
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void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
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uint32_t triggerGroup,
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uint32_t chainGroup,
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const adc_etc_trigger_chain_config_t *config)
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{
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assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
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uint32_t tmp32 = 0U;
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uint32_t tmpReg = 0U;
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uint8_t mRemainder = (uint8_t)(chainGroup % 2U);
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/* Set ADC_ETC_TRIGn_CHAINm register. */
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tmp32 = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) |
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ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) |
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ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable);
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if (true == config->enableB2BMode)
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{
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tmp32 |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK;
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}
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#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
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if (true == config->enableIrq)
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{
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tmp32 |= ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK;
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}
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#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
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switch (chainGroup / 2U)
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{
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case 0U: /* Configurate trigger chain0 and chain 1. */
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tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0;
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if (mRemainder == 0U) /* Chain 0. */
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{
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tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK |
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ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK);
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tmpReg |= tmp32;
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}
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else /* Chain 1. */
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{
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tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK |
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ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK);
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tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT);
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}
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base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmpReg;
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break;
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case 1U: /* Configurate trigger chain2 and chain 3. */
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tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2;
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if (mRemainder == 0U) /* Chain 2. */
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{
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tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK |
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ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK);
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tmpReg |= tmp32;
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}
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else /* Chain 3. */
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{
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tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK |
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ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK);
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tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT);
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}
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base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmpReg;
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break;
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case 2U: /* Configurate trigger chain4 and chain 5. */
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tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4;
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if (mRemainder == 0U) /* Chain 4. */
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{
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tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK |
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ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK);
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tmpReg |= tmp32;
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}
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else /* Chain 5. */
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{
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tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK |
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ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK);
|
||
|
|
tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT);
|
||
|
|
}
|
||
|
|
base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmpReg;
|
||
|
|
break;
|
||
|
|
case 3U: /* Configurate trigger chain6 and chain 7. */
|
||
|
|
tmpReg = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6;
|
||
|
|
if (mRemainder == 0U) /* Chain 6. */
|
||
|
|
{
|
||
|
|
tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK |
|
||
|
|
ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK);
|
||
|
|
tmpReg |= tmp32;
|
||
|
|
}
|
||
|
|
else /* Chain 7. */
|
||
|
|
{
|
||
|
|
tmpReg &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK |
|
||
|
|
ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK);
|
||
|
|
tmpReg |= (tmp32 << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT);
|
||
|
|
}
|
||
|
|
base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmpReg;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
assert(false);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Gets the interrupt status flags of external XBAR and TSC triggers.
|
||
|
|
*
|
||
|
|
* param base ADC_ETC peripheral base address.
|
||
|
|
* param sourceIndex trigger source index.
|
||
|
|
*
|
||
|
|
* return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
|
||
|
|
*/
|
||
|
|
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
|
||
|
|
{
|
||
|
|
uint32_t tmp32 = 0U;
|
||
|
|
|
||
|
|
if (((base->DONE0_1_IRQ) & ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << (uint32_t)sourceIndex)) != 0U)
|
||
|
|
{
|
||
|
|
tmp32 |= (uint32_t)kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in
|
||
|
|
fsl_adc_etc.h file. */
|
||
|
|
}
|
||
|
|
if (((base->DONE0_1_IRQ) & ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << (uint32_t)sourceIndex)) != 0U)
|
||
|
|
{
|
||
|
|
tmp32 |= (uint32_t)kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in
|
||
|
|
fsl_adc_etc.h file. */
|
||
|
|
}
|
||
|
|
if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex)) != 0U)
|
||
|
|
{
|
||
|
|
tmp32 |= (uint32_t)kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in
|
||
|
|
fsl_adc_etc.h file. */
|
||
|
|
}
|
||
|
|
#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
|
||
|
|
if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex)) != 0U)
|
||
|
|
{
|
||
|
|
tmp32 |= (uint32_t)kADC_ETC_Done3StatusFlagMask; /* Customized DONE3 status flags mask, which is defined in
|
||
|
|
fsl_adc_etc.h file. */
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
|
||
|
|
if (((base->DONE2_3_ERR_IRQ) & ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex)) != 0U)
|
||
|
|
{
|
||
|
|
tmp32 |= (uint32_t)kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in
|
||
|
|
fsl_adc_etc.h file. */
|
||
|
|
}
|
||
|
|
return tmp32;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Clears the ADC_ETC's interrupt status falgs.
|
||
|
|
*
|
||
|
|
* param base ADC_ETC peripheral base address.
|
||
|
|
* param sourceIndex trigger source index.
|
||
|
|
* param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
|
||
|
|
*/
|
||
|
|
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
|
||
|
|
{
|
||
|
|
if (0U != (mask & (uint32_t)kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
|
||
|
|
{
|
||
|
|
base->DONE0_1_IRQ = ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << (uint32_t)sourceIndex);
|
||
|
|
}
|
||
|
|
if (0U != (mask & (uint32_t)kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */
|
||
|
|
{
|
||
|
|
base->DONE0_1_IRQ = ((uint32_t)ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << (uint32_t)sourceIndex);
|
||
|
|
}
|
||
|
|
if (0U != (mask & (uint32_t)kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */
|
||
|
|
{
|
||
|
|
base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK << (uint32_t)sourceIndex);
|
||
|
|
}
|
||
|
|
#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
|
||
|
|
if (0U != (mask & (uint32_t)kADC_ETC_Done3StatusFlagMask)) /* Write 1 to clear DONE3 status flags. */
|
||
|
|
{
|
||
|
|
base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK << (uint32_t)sourceIndex);
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
|
||
|
|
if (0U != (mask & (uint32_t)kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */
|
||
|
|
{
|
||
|
|
base->DONE2_3_ERR_IRQ = ((uint32_t)ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK << (uint32_t)sourceIndex);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Get ADC conversion result from external XBAR sources.
|
||
|
|
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
|
||
|
|
* return Trigger0 source's chain1 conversion result.
|
||
|
|
*
|
||
|
|
* param base ADC_ETC peripheral base address.
|
||
|
|
* param triggerGroup Trigger group index. Available number is 0~7.
|
||
|
|
* param chainGroup Trigger chain group index. Available number is 0~7.
|
||
|
|
* return ADC conversion result value.
|
||
|
|
*/
|
||
|
|
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
|
||
|
|
{
|
||
|
|
assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);
|
||
|
|
|
||
|
|
uint32_t mADCResult;
|
||
|
|
uint8_t mRemainder = (uint8_t)(chainGroup % 2U);
|
||
|
|
|
||
|
|
switch (chainGroup / 2U)
|
||
|
|
{
|
||
|
|
case 0U:
|
||
|
|
if (0U == mRemainder)
|
||
|
|
{
|
||
|
|
mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case 1U:
|
||
|
|
if (0U == mRemainder)
|
||
|
|
{
|
||
|
|
mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case 2U:
|
||
|
|
if (0U == mRemainder)
|
||
|
|
{
|
||
|
|
mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case 3U:
|
||
|
|
if (0U == mRemainder)
|
||
|
|
{
|
||
|
|
mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
mADCResult = 0U;
|
||
|
|
assert(false);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return mADCResult;
|
||
|
|
}
|