rt-thread-official/bsp/cvitek/drivers/drv_pwm.c

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2024-03-02 16:16:22 +08:00
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024/02/19 flyingcys first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "drv_pwm.h"
#include "drv_pinmux.h"
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#define DBG_LEVEL DBG_LOG
#include <rtdbg.h>
#define LOG_TAG "DRV.PWM"
struct cvi_pwm_dev
{
struct rt_device_pwm device;
const char *name;
rt_ubase_t reg_base;
};
static const uint64_t count_unit = 100000000; // 100M count per second
static const uint64_t NSEC_COUNT = 1000000000; // ns
static void cvi_pwm_set_config(rt_ubase_t reg_base, struct rt_pwm_configuration *cfg)
{
unsigned long long duty_clk, period_clk;
cvi_pwm_set_polarity_high_ch(reg_base, (cfg->channel & PWM_MAX_CH));
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duty_clk = (cfg->pulse * count_unit) / NSEC_COUNT;
cvi_pwm_set_high_period_ch(reg_base, (cfg->channel & PWM_MAX_CH), duty_clk);
period_clk = (cfg->period * count_unit) / NSEC_COUNT;
cvi_pwm_set_period_ch(reg_base, (cfg->channel & PWM_MAX_CH), period_clk);
cvi_pwm_output_en_ch(reg_base, cfg->channel & PWM_MAX_CH);
}
static void cvi_pwm_get_config(rt_ubase_t reg_base, struct rt_pwm_configuration *cfg)
{
unsigned long long duty_clk, period_clk;
duty_clk = cvi_pwm_get_high_period_ch(reg_base, (cfg->channel & PWM_MAX_CH));
cfg->pulse = duty_clk * NSEC_COUNT / count_unit;
period_clk = cvi_pwm_get_period_ch(reg_base, (cfg->channel & PWM_MAX_CH));
cfg->period = period_clk * NSEC_COUNT / count_unit;
}
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
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static rt_err_t _pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
struct cvi_pwm_dev *pwm_dev = (struct cvi_pwm_dev *)device->parent.user_data;
unsigned long long duty_clk, period_clk;
const uint64_t count_unit = 100000000; // 100M count per second
const uint64_t NSEC_COUNT = 1000000000; // ns
Accumulated patchsets for bsp/cvitek (#8968) * bsp: cvitek: kconfig: add wdt for cv18xx_riscv Add Watchdog timer in Kconfig. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * drv: cvitek: remove using macro from source file Building of source file should be controlled by SConscript, but not in source file itself. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add i2c for cv18xx_riscv Add I2C in Kconfig for c906B. Note, the IRQ# is different from that of c906L. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: kconfig: add rtc for cv18xx_riscv Add RTC in Kconfig for c906B. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: cvitek: fix channel issue for pwm driver The original code confuses the concepts of controllers and channels. Fixed it and do some code cleanup. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for cv18xx_riscv Pinmux in driver code is controlled by SOC type, bcos driver code should be general and support all pins defined by SoC. Pinmux configuration in Kconfig is controlled by BOARD type, bcos when we operate on board, it does not expose all chip-level pin signals and we can only use part of them. Following is I2C signals exported by duo family. Details see https://milkv.io/docs/duo/overview. Note: we have not added support for duo-S. Duo === NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo 256m ======== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S ===== NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME> ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> * bsp:cvitek: remove using macro from source file for i2c Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: unify menu message text for i2c as other drivers Other dirvers has no extra word "HW". Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp:cvitek: add i2c pinmux config for c906_little Porting what we have done in commit "bsp:cvitek: add i2c pinmux config for cv18xx_riscv" to c906_little. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: flyingcys <flyingcys@163.com> Co-authored-by: flyingcys <flyingcys@163.com>
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if (cfg->channel >= PWM_CHANNEL_NUM)
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return -RT_EINVAL;
switch (cmd)
{
case PWM_CMD_ENABLE:
cvi_pwm_start_en_ch(pwm_dev->reg_base, cfg->channel & PWM_MAX_CH);
break;
case PWM_CMD_DISABLE:
cvi_pwm_start_dis_ch(pwm_dev->reg_base, cfg->channel & PWM_MAX_CH);
break;
case PWM_CMD_SET:
cvi_pwm_set_config(pwm_dev->reg_base, cfg);
break;
case PWM_CMD_GET:
cvi_pwm_get_config(pwm_dev->reg_base, cfg);
break;
case PWM_CMD_SET_PERIOD:
period_clk = (cfg->period * count_unit) / NSEC_COUNT;
cvi_pwm_set_period_ch(pwm_dev->reg_base, (cfg->channel & PWM_MAX_CH), period_clk);
break;
case PWM_CMD_SET_PULSE:
duty_clk = (cfg->pulse * count_unit) / NSEC_COUNT;
cvi_pwm_set_high_period_ch(pwm_dev->reg_base, (cfg->channel & PWM_MAX_CH), duty_clk);
break;
default:
LOG_D("cmd: %x channel: %d period: %d pulse: %d", cmd, cfg->channel, cfg->period, cfg->pulse);
break;
}
return RT_EOK;
}
const static struct rt_pwm_ops cvi_pwm_ops =
{
.control = &_pwm_control
};
static struct cvi_pwm_dev cvi_pwm[] =
{
#ifdef BSP_USING_PWM0
{
.name = "pwm0",
.reg_base = CVI_PWM0_BASE,
},
#endif
#ifdef BSP_USING_PWM1
{
.name = "pwm1",
.reg_base = CVI_PWM1_BASE,
},
#endif
#ifdef BSP_USING_PWM2
{
.name = "pwm2",
.reg_base = CVI_PWM2_BASE,
},
#endif
#ifdef BSP_USING_PWM3
{
.name = "pwm3",
.reg_base = CVI_PWM3_BASE,
},
#endif
};
#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR)
#ifdef BSP_USING_PWM0
static const char *pinname_whitelist_pwm0[] = {
NULL,
};
static const char *pinname_whitelist_pwm1[] = {
NULL,
};
static const char *pinname_whitelist_pwm2[] = {
NULL,
};
static const char *pinname_whitelist_pwm3[] = {
NULL,
};
#endif
#ifdef BSP_USING_PWM1
static const char *pinname_whitelist_pwm4[] = {
"SD1_D3",
"UART0_TX",
NULL,
};
static const char *pinname_whitelist_pwm5[] = {
"SD1_D2",
"UART0_RX",
NULL,
};
static const char *pinname_whitelist_pwm6[] = {
"SD1_D1",
NULL,
};
static const char *pinname_whitelist_pwm7[] = {
"SD1_D0",
NULL,
};
#endif
#ifdef BSP_USING_PWM2
static const char *pinname_whitelist_pwm8[] = {
"SD1_CMD",
NULL,
};
static const char *pinname_whitelist_pwm9[] = {
"SD1_CLK",
NULL,
};
static const char *pinname_whitelist_pwm10[] = {
"SD1_GPIO1",
NULL,
};
static const char *pinname_whitelist_pwm11[] = {
"SD1_GPIO0",
NULL,
};
#endif
#ifdef BSP_USING_PWM3
static const char *pinname_whitelist_pwm12[] = {
NULL,
};
static const char *pinname_whitelist_pwm13[] = {
NULL,
};
static const char *pinname_whitelist_pwm14[] = {
NULL,
};
static const char *pinname_whitelist_pwm15[] = {
NULL,
};
#endif
#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR)
#ifdef BSP_USING_PWM0
static const char *pinname_whitelist_pwm0[] = {
NULL,
};
static const char *pinname_whitelist_pwm1[] = {
NULL,
};
static const char *pinname_whitelist_pwm2[] = {
NULL,
};
static const char *pinname_whitelist_pwm3[] = {
NULL,
};
#endif
#ifdef BSP_USING_PWM1
static const char *pinname_whitelist_pwm4[] = {
"SD1_D3",
"UART0_TX",
NULL,
};
static const char *pinname_whitelist_pwm5[] = {
"SD1_D2",
"UART0_RX",
NULL,
};
static const char *pinname_whitelist_pwm6[] = {
"JTAG_CPU_TCK",
"SD1_D1",
NULL,
};
static const char *pinname_whitelist_pwm7[] = {
"JTAG_CPU_TMS",
"SD1_D0",
NULL,
};
#endif
#ifdef BSP_USING_PWM2
static const char *pinname_whitelist_pwm8[] = {
"SD1_CMD",
NULL,
};
static const char *pinname_whitelist_pwm9[] = {
"SD1_CLK",
NULL,
};
static const char *pinname_whitelist_pwm10[] = {
"PAD_MIPI_TXM1",
NULL,
};
static const char *pinname_whitelist_pwm11[] = {
"PAD_MIPI_TXP1",
NULL,
};
#endif
#ifdef BSP_USING_PWM3
static const char *pinname_whitelist_pwm12[] = {
NULL,
};
static const char *pinname_whitelist_pwm13[] = {
NULL,
};
static const char *pinname_whitelist_pwm14[] = {
NULL,
};
static const char *pinname_whitelist_pwm15[] = {
NULL,
};
#endif
#else
#error "Unsupported board type!"
#endif
static void rt_hw_pwm_pinmux_config()
{
#ifdef BSP_USING_PWM0
pinmux_config(BSP_PWM0_0_PINNAME, PWM_0, pinname_whitelist_pwm0);
pinmux_config(BSP_PWM0_1_PINNAME, PWM_1, pinname_whitelist_pwm1);
pinmux_config(BSP_PWM0_2_PINNAME, PWM_2, pinname_whitelist_pwm2);
pinmux_config(BSP_PWM0_3_PINNAME, PWM_3, pinname_whitelist_pwm3);
#endif /* BSP_USING_PWM0 */
#ifdef BSP_USING_PWM1
pinmux_config(BSP_PWM1_4_PINNAME, PWM_4, pinname_whitelist_pwm4);
pinmux_config(BSP_PWM1_5_PINNAME, PWM_5, pinname_whitelist_pwm5);
pinmux_config(BSP_PWM1_6_PINNAME, PWM_6, pinname_whitelist_pwm6);
pinmux_config(BSP_PWM1_7_PINNAME, PWM_7, pinname_whitelist_pwm7);
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
pinmux_config(BSP_PWM2_8_PINNAME, PWM_8, pinname_whitelist_pwm8);
pinmux_config(BSP_PWM2_9_PINNAME, PWM_9, pinname_whitelist_pwm9);
pinmux_config(BSP_PWM2_10_PINNAME, PWM_10, pinname_whitelist_pwm10);
pinmux_config(BSP_PWM2_11_PINNAME, PWM_11, pinname_whitelist_pwm11);
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
pinmux_config(BSP_PWM3_12_PINNAME, PWM_12, pinname_whitelist_pwm12);
pinmux_config(BSP_PWM3_13_PINNAME, PWM_13, pinname_whitelist_pwm13);
pinmux_config(BSP_PWM3_14_PINNAME, PWM_14, pinname_whitelist_pwm14);
pinmux_config(BSP_PWM3_15_PINNAME, PWM_15, pinname_whitelist_pwm15);
#endif /* BSP_USING_PWM3 */
}
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int rt_hw_pwm_init(void)
{
int result = RT_EOK;
uint8_t i;
rt_hw_pwm_pinmux_config();
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for (i = 0; i < sizeof(cvi_pwm) / sizeof(cvi_pwm[0]); i++)
{
result = rt_device_pwm_register(&cvi_pwm[i].device, cvi_pwm[i].name, &cvi_pwm_ops, &cvi_pwm[i]);
if (result != RT_EOK)
{
LOG_E("device %s register failed", cvi_pwm[i].name);
return -RT_ERROR;
}
}
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_pwm_init);